Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
02/2008
02/21/2008WO2008005944A3 Systems and methods for alignment of laser beam (s) for semiconductor link processing
02/21/2008WO2008005695A3 Memory device with speculative commands to memory core
02/21/2008US20080046802 Memory controller and method of controlling memory
02/21/2008US20080046798 Method and system for reducing volatile dram power budget
02/21/2008US20080046788 Semiconductor memory device
02/21/2008US20080046780 Nonvolatile memory
02/21/2008US20080046759 ID installable LSI, secret key installation method, LSI test method, and LSI development method
02/21/2008US20080046643 Memory card
02/21/2008US20080043551 Electrical fuse circuit, memory device and electronic part
02/21/2008US20080043550 Semiconductor memory device
02/20/2008EP1890298A1 Test method for semiconductor memory circuit
02/20/2008EP1890297A1 Test method for semiconductor memory circuit
02/20/2008EP1890294A2 Buffered memory module with configurable interface width
02/20/2008EP1890239A1 Memory contoller and method of controlling memory
02/20/2008EP1889294A1 One-time programmable crosspoint memory with a diode as an antifuse
02/20/2008CN201025531Y BCH coding random error detection and correction device
02/20/2008CN101128882A Single wafer magnetic resistance type memory
02/20/2008CN101128803A Enabling special modes within a digital device
02/20/2008CN101127246A Electric fuse circuit and electronic component
02/20/2008CN101127245A Electrical fuse circuit, memory device and electronic part
02/20/2008CN101127244A Semiconductor memory device containing antifuse write voltage generation circuit
02/20/2008CN101127243A Memory controller and method of controlling memory
02/20/2008CN101127242A Semiconductor memory and system
02/20/2008CN100370614C Semiconductor integrated circuit device and method for controlling semiconductor integrated circuit device
02/19/2008US7334179 Method and system for detecting and correcting errors while accessing memory devices in microprocessor systems
02/19/2008US7334174 Semiconductor integrated circuit device and error detecting method therefor
02/19/2008US7334170 Method for resolving parameters of DRAM
02/19/2008US7334168 Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit
02/19/2008US7334159 Self-testing RAM system and method
02/19/2008US7333385 Semiconductor memory device having the operating voltage of the memory cell controlled
02/19/2008US7333384 Techniques for storing accurate operating current values
02/19/2008US7333377 Test mode control device using nonvolatile ferroelectric memory
02/19/2008US7333376 Test mode control device using nonvolatile ferroelectric memory
02/19/2008US7333375 Repair control circuit of semiconductor memory device with reduced size
02/19/2008US7333374 Semiconductor memory device capable of replacing defective memory cell with redundant memory cell, and electronic equipment
02/19/2008US7333360 Apparatus for pulse testing a MRAM device and method therefore
02/14/2008WO2008019252A1 Systems and methods for distinguishing reflections of multiple laser beams for calibration for semiconductor structure processing
02/14/2008US20080040646 Raid environment incorporating hardware-based finite field multiplier for on-the-fly xor
02/14/2008US20080040645 Error Correction For Disk Storage Media
02/14/2008US20080040531 Data storage device
02/14/2008US20080037341 Enabling memory redundancy during testing
02/14/2008US20080037340 Apparatus for testing a memory of an integrated circuit
02/14/2008US20080037339 Memory array for an integrated circuit
02/14/2008US20080037325 On-chip ee-prom programming waveform generation
02/14/2008US20080037319 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
02/14/2008US20080037318 Thin film magnetic memory device having redundant configuration
02/14/2008DE60220511T2 Verfahren und system zur optimierung der testkosten und deaktivierungsdefekte für scan- und bist-speicher Method and system for optimizing the test cost and deactivation defective for scan- and are mem
02/14/2008DE102007034277A1 Vorrichtung und Verfahren zum Erzeugen von Test-Strukturdaten zum Testen eines Halbleiterbauelements Apparatus and method for generating test data structure for testing a semiconductor device
02/14/2008DE102007033785A1 Speichersteuereinheit, DDR-Speichersteuereinheit und Verfahren zum Testen einer Speichersteuereinheit Memory controller, DDR memory control unit and method for testing a memory controller
02/13/2008EP1887582A2 Semiconductor memory with redundant rows and columns and a flexible redundancy architecture
02/13/2008EP1886351A2 Apparatus and methods for maintaining integrated circuit performance at reduced power
02/13/2008EP1886321A1 Memory device with row shifting for defective row repair
02/13/2008EP1886155A2 Memory device and method having a data bypass path to allow rapid testing and calibration
02/13/2008EP1029278B1 Moving sequential sectors within a block of information in a flash memory mass storage architecture
02/13/2008CN101124639A System and method of accessing non-volatile computer memory
02/13/2008CN101123123A Semiconductor memory device capable of changing ecc code length
02/13/2008CN100369225C Testing apparatus, system and method for testing contact between semiconductor and carrier
02/13/2008CN100369159C Detection method of flash storage
02/13/2008CN100368818C Test module and test method in use for electrical erasable memory built in chip
02/12/2008US7331011 Semiconductor integrated circuit device
02/12/2008US7331010 System, method and storage medium for providing fault detection and correction in a memory subsystem
02/12/2008US7330932 Disk array with spare logic drive created from space physical drives
02/12/2008US7330909 External storage subsystem
02/12/2008US7330385 Integrated semiconductor memory device with adaptation of the evaluation characteristic of sense amplifiers
02/12/2008US7330383 Semiconductor device with a plurality of fuse elements and method for programming the device
02/12/2008US7330045 Semiconductor test apparatus
02/07/2008US20080034335 Design Structures Incorporating Semiconductor Device Structures with Reduced Junction Capacitance and Drain Induced Barrier Lowering
02/07/2008US20080034269 Apparatus and method for recording data in information recording medium to which extra ecc is applied or reproducing data from the medium
02/07/2008US20080034259 Data recorder
02/07/2008US20080034130 Buffered Memory Having A Control Bus And Dedicated Data Lines
02/07/2008US20080031061 System and method for initiating a bad block disable process in a non-volatile memory
02/07/2008US20080031055 Semiconductor memory device capable of performing low-frequency test operation and method for testing the same
02/07/2008DE102007034279A1 Tester zum Testen einer Halbleitervorrichtung Tester for testing a semiconductor device
02/06/2008CN101120417A Erased sector detection mechanisms
02/06/2008CN101118788A Memory controller automatization testing method and apparatus
02/06/2008CN100367412C Semiconductor memory device
02/06/2008CN100367355C Method and apparatus for testing tunnel magnetoresistive effect element
02/06/2008CN100367236C Storage system comprising means managing a storage unit with anti-wear and anti-wear management of a storage unit
02/05/2008US7328392 Disk array system
02/05/2008US7328388 Built-in self-test arrangement for integrated circuit memory devices
02/05/2008US7328382 Memory BISR controller architecture
02/05/2008US7328381 Testing system and method for memory modules having a memory hub architecture
02/05/2008US7328380 Memory scrubbing logic
02/05/2008US7328379 Look-up table for use with redundant memory
02/05/2008US7328378 Repair techniques for memory with multiple redundancy
02/05/2008US7328365 System and method for providing error check and correction in memory systems
02/05/2008US7327766 Circuit configuration for receiving a data signal
02/05/2008US7327647 Method and apparatus for generating the wobble clock signal
02/05/2008US7327624 Storage device employing a flash memory
02/05/2008US7327605 High bandwidth datapath load and test of multi-level memory cells
01/2008
01/31/2008WO2008013340A1 Low power deterministic bist using split lfsr
01/31/2008US20080028278 Circuit architecture protected against perturbations
01/31/2008US20080026510 Nonvolatile memory cell comprising a reduced height vertical diode
01/31/2008US20080025118 Method for using a mixed-use memory array
01/31/2008US20080025115 Method and system for testing semiconductor memory device using internal clock signal of semiconductor memory device as data strobe signal
01/31/2008DE102006035076A1 Integrated semiconductor memory e.g. volatile RAM, has redundant data lines interconnected with data distributor cable over switching unit e.g. transistor, such that redundant data line or group of redundant data lines is selected
01/31/2008DE102006019075B4 Integrierte Schaltung zur Speicherung eines Datums An integrated circuit for storing a datum
01/30/2008CN101114530A Method and apparatus for accessing nonvolatile memory with read error by changing read reference current
01/30/2008CN101114529A Integrated semiconductor memory and method for operating an integrated semiconductor memory
01/30/2008CN101114528A Memory system