Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/2007
11/06/2007US7293216 Bit error position estimation in data decoder
11/06/2007US7293212 Memory self-test via a ring bus in a data processing apparatus
11/06/2007US7293208 Test method for nonvolatile memory
11/06/2007US7293207 Method for testing memory in a computer system utilizing a CPU with either 32-bit or 36-bit memory addressing
11/06/2007US7293197 Non-volatile memory with network fail-over
11/06/2007US7292499 Semiconductor device including duty cycle correction circuit
11/06/2007US7292496 Semiconductor memory circuit
11/06/2007US7292492 SRAM, semiconductor memory device, method for maintaining data in SRAM, and electronic device
11/06/2007US7292489 Circuits and methods of temperature compensation for refresh oscillator
11/06/2007US7292487 Independent polling for multi-page programming
11/06/2007US7292480 Memory card having buffer memory for storing testing instruction
11/06/2007US7292464 Ferroelectric memory device
11/06/2007US7292046 Simulated module load
11/01/2007WO2007103220A3 Calibration system for writing and reading multiple states into phase change memory
11/01/2007US20070256040 Critical area computation of composite fault mechanisms using voronoi diagrams
11/01/2007US20070256000 Redundancy protection for data recorded across multiple layers of recording media
11/01/2007US20070255999 Memory Arrangement And Method For Error Correction
11/01/2007US20070255998 Memory command unit throttle and error recovery
11/01/2007US20070255983 Semiconductor integrated circuit and electronic device
11/01/2007US20070255982 Memory device testing system and method having real time redundancy repair analysis
11/01/2007US20070255981 Redundancy-function-equipped semiconductor memory device made from ECC memory
11/01/2007US20070255919 Memory controller device having timing offset capability
11/01/2007US20070253264 Integrated Semiconductor Memory with a Test Function and Method for Testing an Integrated Semiconductor Memory
11/01/2007US20070253263 Nonvolatile memory device with test mechanism
11/01/2007US20070253252 Memory cell repair using fuse programming method in a memory device
11/01/2007US20070253246 Thin film magnetic memory device provided with program element
11/01/2007US20070252143 Semiconductor memory element and lifetime operation starting apparatus therefor
10/2007
10/31/2007EP1849162A1 A single chip having a magnetoresistive memory
10/31/2007DE19722414B4 Verfahren und Vorrichtung zum Testen eines Halbleiterspeichers Method and apparatus for testing a semiconductor memory
10/31/2007DE102006024215A1 Semiconductor memory device e.g. dynamic RAM, operating method, involves selecting number of data bits corresponding to data item width from memory cells of cell field of device, where selected data bits are combined in groups on data bus
10/31/2007DE102006019908A1 Integrated semiconductor memory e.g. dynamic RAM, has comparator unit comprising input terminals connected with output terminals of memory units, where stored data are readable from memory units depending on state of comparative signal
10/31/2007DE102006019507A1 Integrated semiconductor memory e.g. dynamic RAM, has memory cells attached between ends of bitline, circuit unit with control input for supplying control signal, and controllable switch connected between ends
10/31/2007DE102006019426A1 Error correction method for use in memory arrangement, involves testing whether information is incorrect in one of modules and reading information from other module using address when information is incorrect
10/31/2007DE102006019075A1 Integrated circuit for storing data, has memory circuit with inverter circuits, where strengthening and/or weakening of transistors in corresponding inverter circuits is realized by change of channel lengths and breadths of transistors
10/31/2007CN101065809A Sram test method and SRAM test arrangement to detect weak cells
10/31/2007CN101064195A Dynamic management approach for memory body
10/31/2007CN101064187A Semiconductor integrated circuit
10/31/2007CN101063949A Methods and apparatus for performing memory maintenance
10/31/2007CN100346477C Circuit arrangement for setting a voltage supply for a test mode of an integrated memory
10/31/2007CN100346461C Non-volatile memory evaluating method and non-volatile memory
10/31/2007CN100346422C Semiconductor memory device and control method thereof
10/31/2007CN100346421C Magnetic random access storage device
10/30/2007US7290199 Method and system for improved buffer utilization for disk array parity updates
10/30/2007US7290198 Memory card and memory controller
10/30/2007US7290197 Correcting data using redundancy blocks
10/30/2007US7290186 Method and apparatus for a command based bist for testing memories
10/30/2007US7290184 Emulation system for evaluating digital data channel configurations
10/30/2007US7290179 System and method for soft error handling
10/30/2007US7290097 Nonvolatile memory
10/30/2007US7289380 Semiconductor memory devices incorporating voltage level shifters for controlling a VPP voltage level independently and methods of operating the same
10/30/2007US7289364 Programmable memory device with an improved redundancy structure
10/25/2007WO2007119485A1 Test device and test method
10/25/2007US20070250757 Method and data storage devices for a RAID system
10/25/2007US20070250756 High reliability memory module with a fault tolerant address and command bus
10/25/2007US20070250755 Dormant error checker
10/25/2007US20070250746 Testing CMOS ternary CAM with redundancy
10/25/2007US20070250745 Method and system for testing a memory device
10/25/2007US20070250744 Method and apparatus for testing the connectivity of a flash memory chip
10/25/2007US20070247937 Information processing system for calculating the number of redundant lines optimal for memory device
10/25/2007US20070247936 Flexible and efficient memory utilization for high bandwidth receivers, integrated circuits, systems, methods and processes of manufacture
10/25/2007DE19860871B4 Leistungsunabhängiger Halbleiterspeicherbaustein und Verfahren zur Ansteuerung von dessen Wortleitungen Independent power semiconductor memory device and method for controlling the word lines
10/25/2007DE102007018342A1 Semiconductor memory device testing device, has address supply circuit supplying memory input bits with memory input addresses to semiconductor memory device, where memory input bits are inputted by logical operation circuits
10/25/2007DE102005053625B4 Speichermodul mit einer Mehrzahl von Speicherbausteinen Storage module having a plurality of memory devices
10/24/2007EP1848001A1 Soft error location and sensitivity detection for programmable devices
10/24/2007CN101061549A System and method for expanding a pulse width
10/24/2007CN101060015A A multi-bit flash memory and its error detection and remedy method
10/24/2007CN101060014A A method and device for detecting the physical parameters of flash memory
10/24/2007CN101060008A Multi-port memory device with serial input/output interface and control method thereof
10/24/2007CN101060006A Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode
10/24/2007CN101059752A Storage device using nonvolatile cache memory and control method thereof
10/24/2007CN100345269C Apparatus for testing semiconductor device
10/24/2007CN100345219C Testing method of embedding DRAM array
10/24/2007CN100344983C Semiconductor testing circuit, semiconductor storage and semiconductor testing method
10/23/2007US7287204 Memory unit test
10/23/2007US7287203 Testing embedded RAM blocks by employing RAM scan techniques
10/23/2007US7287202 Method and apparatus for testing a memory interface
10/23/2007US7287142 Memory device and method for arbitrating internal and external access
10/23/2007US7286431 Memory device capable of performing high speed reading while realizing redundancy replacement
10/23/2007US7286426 Semiconductor memory device
10/23/2007US7286424 Semiconductor integrated circuit device
10/23/2007US7286422 Memory device with built-in test function and method for controlling the same
10/23/2007US7286421 Active compensation for operating point drift in MRAM write operation
10/23/2007US7286420 Semiconductor memory device
10/23/2007US7286399 Dedicated redundancy circuits for different operations in a flash memory device
10/23/2007US7285464 Nonvolatile memory cell comprising a reduced height vertical diode
10/18/2007WO2007116503A1 Integrated circuit device, manufacturing device, and manufacturing method
10/18/2007US20070245218 Semiconductor integrated circuit and record player
10/18/2007US20070245190 Intelligent binning for electrically repairable semiconductor chips
10/18/2007US20070245182 Semiconductor memory device
10/18/2007US20070245181 Memory system and method of writing into nonvolatile semiconductor memory
10/18/2007US20070245180 Circuitry and method for an at-speed scan test
10/18/2007US20070245179 Manufacturing method of semiconductor device and semiconductor device corresponding to loop back test
10/18/2007US20070245178 Parallel processing apparatus dynamically switching over circuit configuration
10/18/2007US20070245168 Associative memory capable of searching for data while keeping high data reliability
10/18/2007US20070244660 Alternator tester
10/18/2007US20070242506 Semiconductor memory device storing redundant replacement information with small occupation area
10/18/2007US20070242494 Memory array with readout isolation
10/18/2007DE102007007854A1 Verfahren und Vorrichtung für einen Oszillator in einem Speicherbaustein Method and apparatus for an oscillator in a memory module
10/18/2007DE102007001075A1 Multiport-Speichervorrichtung mit serieller Eingabe-/Ausgabe-Schnittstelle und Steuerverfahren davon Multi-port memory device with serial input / output interface and control method thereof
10/18/2007DE102006062024A1 Multi port semiconductor memory device, has test mode control device executing core test by converting serial data communication into parallel data communication during selected core test mode, where control device has mode adjusting unit
1 ... 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 ... 306