| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
|---|
| 08/19/2008 | US7415640 Methods and apparatuses that reduce the size of a repair data container for repairable memories |
| 08/19/2008 | US7415633 Method and apparatus for preventing and recovering from TLB corruption by soft error |
| 08/19/2008 | US7414914 Semiconductor memory device |
| 08/19/2008 | US7414903 Nonvolatile memory device with test mechanism |
| 08/19/2008 | US7414902 Semiconductor memory device with information loss self-detect capability |
| 08/19/2008 | US7414897 Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device |
| 08/19/2008 | US7414894 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance |
| 08/14/2008 | US20080195916 Method and apparatus of correcting error data caused by charge loss within non-volatile memory device |
| 08/14/2008 | US20080195903 Non-volatile memory device with built-in test control unit and methods of testing and repairing a cell array |
| 08/14/2008 | US20080195902 Method, Apparatus and Program Product to Concurrently Detect, Repair, Verify and Isolate Memory Failures |
| 08/14/2008 | US20080195901 Op-code based built-in-self-test |
| 08/14/2008 | US20080195900 Flash memory system and method for controlling the same |
| 08/14/2008 | US20080195823 Method and apparatus for convolutional interleaving/de-interleaving technique |
| 08/14/2008 | US20080191355 Semiconductor device having buffer layer pattern and method of forming same |
| 08/14/2008 | DE102008008464A1 Verfahren und Vorrichtung zum Auswählen von redundanten Speicherzellen Method and apparatus for selecting redundant memory cells |
| 08/14/2008 | DE102007050430A1 Verfahren für das Steuern eines Speicherzugriffs A method for controlling a memory access, |
| 08/14/2008 | DE102007006385A1 Circuit arrangement for e.g. personal computer, has scan-test and data input layers with respective inputs for inputting test and input signals, and latch coupled with respective output of scan test and data input layers |
| 08/13/2008 | CN101241770A Defect analysis methods for semiconductor integrated circuit devices and defect analysis systems |
| 08/13/2008 | CN101241769A A repairable semiconductor memory device and method of repairing the same |
| 08/13/2008 | CN101241768A Memory device employing dual clocking for generating systematic code and method thereof |
| 08/13/2008 | CN101241767A Nonvolatile semiconductor storage device and method of managing the same |
| 08/13/2008 | CN101241751A Semiconductor device and method of testing semiconductor device |
| 08/13/2008 | CN100411173C Layered power source noise monitoring device of ultra large scale integrated circuit and system |
| 08/13/2008 | CN100410889C Method for testing physical memory |
| 08/12/2008 | US7412627 Method and apparatus for providing debug functionality in a buffered memory channel |
| 08/12/2008 | US7411848 Independent polling for multi-page programming |
| 08/12/2008 | US7411847 Burn in system and method for improved memory reliability |
| 08/12/2008 | US7411844 Semiconductor memory device having a redundancy information memory directly connected to a redundancy control circuit |
| 08/12/2008 | US7411809 Ferroelectric memory to be tested by applying disturbance voltage to a plurality of ferroelectric capacitors at once in direction to weaken polarization, and method of testing the same |
| 08/07/2008 | WO2008093807A1 Monitor burn-in test device and monitor burn-in test method |
| 08/07/2008 | WO2008033693A3 Non-volatile memory and method for linear estimation of initial programming voltage |
| 08/07/2008 | US20080189588 Bit error prevention method and information processing apparatus |
| 08/07/2008 | US20080189582 Analysis techniques for multi-level memory |
| 08/07/2008 | US20080186785 Semiconductor memory device for preventing supply of excess specific stress item and test method thereof |
| 08/07/2008 | US20080186784 Testing for sram memory data retention |
| 08/07/2008 | DE102007004638A1 Integrierter Halbleiterspeicher und Verfahren zum Betreiben eines Datenpfads in einem Halbleiterspeicher Integrated semiconductor memory and method of operating a data path in a semiconductor memory, |
| 08/07/2008 | DE102007004311A1 Halbleiter-Bauelement, insbesondere DRAM, mit mehreren verschiedenartigen einmal-programmierbaren Elementen Semiconductor component, in particular DRAM, with several different types of one-time programmable elements |
| 08/06/2008 | EP1953762A1 Memory device with reduced standby power consumption and method for operating same |
| 08/06/2008 | EP1952290A2 Probabilistic error correction in multi-bit-per-cell flash memory |
| 08/06/2008 | CN101236791A Method, circuit and apparatus for multi-segment SRAM |
| 08/06/2008 | CN101236790A Chip with integrated read-only memory and built-in self-test system and its method |
| 08/06/2008 | CN101236789A Method and apparatus for detecting static data area, wear-leveling, and merging data units |
| 08/06/2008 | CN100409366C Storage circuit with redundant structure |
| 08/06/2008 | CN100409364C Semiconductor storage equipment with storage unit array which is divided into block |
| 08/06/2008 | CN100409362C Memory device, method for amplifying its bit line, and control device for sensing margin time |
| 08/06/2008 | CN100409193C Nonvolatile memory device and data processing system |
| 08/05/2008 | US7409625 Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array |
| 08/05/2008 | US7409624 Memory command unit throttle and error recovery |
| 08/05/2008 | US7409623 System and method of reading non-volatile computer memory |
| 08/05/2008 | US7409610 Total configuration memory cell validation built in self test (BIST) circuit |
| 08/05/2008 | US7409607 Memory address generating apparatus, processor having the same, and memory address generating method |
| 08/05/2008 | US7408863 Digital signal processing method, data recording and reproducing apparatus, and data recording medium that are resistant to burst errors |
| 08/05/2008 | US7408824 Ferroelectric memory with spare memory cell array and ECC circuit |
| 07/31/2008 | US20080184096 Repair Techniques for Memory with Multiple Redundancy |
| 07/31/2008 | US20080184094 Programming management data for NAND memories |
| 07/31/2008 | US20080184093 Error correction algorithm selection based upon memory organization |
| 07/31/2008 | US20080181045 Calibration circuit of a semiconductor memory device and method of operating the same |
| 07/31/2008 | US20080181037 Multi-port semiconductor memory device |
| 07/31/2008 | US20080181036 Method of testing semiconductor apparatus |
| 07/31/2008 | US20080181035 Method and system for a dynamically repairable memory |
| 07/31/2008 | US20080181002 Charge loss restoration method and semiconductor memory device |
| 07/31/2008 | DE10354112B4 Verfahren und Anordnung zur Reparatur von Speicherchips mittels Mikro-Lithographie-Verfahren Method and apparatus for repairing memory chips using micro-lithography process |
| 07/31/2008 | DE102008003043A1 Speicher mit Fehlerkorrekturcodeschaltung Memory with error correction code circuit |
| 07/31/2008 | DE102004036888B4 Flashspeichersystem und zugehöriges Datenschreibverfahren Flash memory system and associated data writing method |
| 07/30/2008 | CN101231892A Nonvolatile semiconductor memory and method of access evaluation to the same |
| 07/30/2008 | CN101231891A Error control method and memory system |
| 07/30/2008 | CN100407337C 管理闪存中的不良存储块的装置和方法 Management apparatus and method for flash memory of the bad memory block |
| 07/30/2008 | CN100407334C 非易失性半导体存储器及其操作方法 The nonvolatile semiconductor memory device and method of operation |
| 07/30/2008 | CN100406902C 有针对性应用的基于事件的半导体存储器测试系统 Semiconductor memory test system targeted event-based applications |
| 07/29/2008 | US7406649 Semiconductor memory device and signal processing system |
| 07/29/2008 | US7406643 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium |
| 07/29/2008 | US7406637 Semiconductor memory device capable of testing memory cells at high speed |
| 07/29/2008 | US7405985 Flexible and area efficient column redundancy for non-volatile memories |
| 07/29/2008 | CA2347765C Column redundancy circuit with reduced signal path delay |
| 07/24/2008 | WO2008089157A2 Column leakage compensation in a sensing circuit |
| 07/24/2008 | WO2008088615A2 Memory device and method of making same |
| 07/24/2008 | WO2008087082A1 Method and apparatus for recording data into a matrix of memory devices |
| 07/24/2008 | WO2008033679A3 Non-volatile memory and method for reduced erase/write cycling during trimming of initial programming voltage |
| 07/24/2008 | US20080178061 Segregation of redundant control bits in an ecc permuted, systematic modulation code |
| 07/24/2008 | US20080178054 Test circuits of semiconductor memory device for multi-chip testing and method for testing multi chips |
| 07/24/2008 | US20080178053 Hybrid built-in self test (bist) architecture for embedded memory arrays and an associated method |
| 07/24/2008 | US20080175080 Semiconductor memory device and test method thereof |
| 07/24/2008 | US20080175079 Test scheme for fuse circuit |
| 07/24/2008 | US20080175054 Methods and systems for memory devices |
| 07/24/2008 | US20080174336 Circuit and method for detecting skew of transistor in semiconductor device |
| 07/24/2008 | DE112006002519T5 Prüfvorrichtung, Prüfverfahren, Analysevorrichtung und -programm Tester, test methods, apparatus and program analysis |
| 07/24/2008 | DE112006002421T5 Halbleiterspeicherbauelement mit Bitregisterschicht und Verfahren zum Steuern derselben The semiconductor memory device with Bitregisterschicht and method for controlling the same |
| 07/23/2008 | EP1947652A1 Phase-change memory device with error correction capability |
| 07/23/2008 | EP1947651A2 Semiconductor memory |
| 07/23/2008 | EP1946326A1 Memory with retargetable memory cell redundancy |
| 07/23/2008 | EP1859452A4 Multiply redundant raid system and xor-efficient implementation |
| 07/23/2008 | CN101226778A Semiconductor memory having function to determine semiconductor low current |
| 07/23/2008 | CN101226777A Storage apparatus and apparatus with reduced test stitch as well as test approach thereof |
| 07/23/2008 | CN101226776A Performance control of an integrated circuit |
| 07/23/2008 | CN101226774A Method for reducing data error in flash memory device when using copy back instruction |
| 07/23/2008 | CN100405503C Redundant contrl circuit of true programmed prgram unit and semiconductor storage using it |
| 07/23/2008 | CN100405074C Test terminal negation circuit |
| 07/22/2008 | US7404159 Critical area computation of composite fault mechanisms using Voronoi diagrams |
| 07/22/2008 | US7404137 Method and related apparatus for performing error checking-correcting |
| 07/22/2008 | US7404131 High efficiency, error minimizing coding strategy method and apparatus |