Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
07/2008
07/01/2008US7395464 Memory circuit having a controllable output drive
07/01/2008US7395168 Method for evaluating semiconductor device error and system for supporting the same
07/01/2008US7394709 Memory device
07/01/2008US7394691 Semiconductor memory device which prevents destruction of data
07/01/2008US7394688 Nonvolatile memory
07/01/2008US7394476 Methods and systems for thermal-based laser processing a multi-material device
06/2008
06/26/2008WO2008077125A1 Erasing flash memory using adaptive drain and/or gate bias
06/26/2008WO2008076912A1 Method and device for testing memory
06/26/2008WO2008023297A3 Circuit arrangement and method for data processing
06/26/2008WO2007065155A3 Rewrite strategy and methods and systems for error correction in high-density recording
06/26/2008US20080155380 Increasing the Effectiveness of Error Correction Codes and Operating Multi-Level Memory Systems by Using Information About the Quality of the Stored Data
06/26/2008US20080155379 Data Storage Device And Data Processing Method
06/26/2008US20080155377 Method and apparatus for high speed optical recording
06/26/2008US20080155363 Bist circuit device and self test method thereof
06/26/2008US20080155362 Test Structure for Characterizing Multi-Port Static Random Access Memory and Register File Arrays
06/26/2008US20080155138 Datapipe cpu register array
06/26/2008US20080151661 Semiconductor integrated circuit device comprising mos transistor having charge storage layer and method for testing semiconductor memory device
06/26/2008US20080151659 Semiconductor memory device
06/26/2008US20080151653 Semiconductor memory device
06/26/2008US20080151625 Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time
06/26/2008DE102007060266A1 Verfahren und Vorrichtung zum selektiven Nutzen von Informationen in einem Halbleiterbauteil Method and apparatus for selectively using information in a semiconductor device
06/26/2008DE102007058928A1 Verfahren und Halbleiterspeicher mit einer Einrichtung zur Erkennung von Adressierungsfehlern The method and semiconductor memory having a device for detecting addressing errors
06/25/2008CN101208755A Apparatus, system, and method for accessing persistent files in non-execute-in-place flash memory
06/25/2008CN101206924A Control method of flash memory
06/25/2008CN101206921A Method for reducing storage unit write-in disorder
06/25/2008CN101206920A Method for reducing storage unit write-in disorder
06/24/2008US7392515 Program components having multiple selectable implementations
06/24/2008US7392465 Testing ram address decoder for resistive open defects
06/24/2008US7392457 Memory storage device having a nonvolatile memory and memory controller with error check operation mode
06/24/2008US7392456 Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
06/24/2008US7392444 Non-volatile memory evaluating method and non-volatile memory
06/24/2008US7392443 Method and apparatus for testing DRAM memory chips in multichip memory modules
06/24/2008US7392442 Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol
06/24/2008US7391663 Structure and method for measuring the channel boosting voltage of NAND flash memory at a node between drain/source select transistor and adjacent flash memory cell
06/24/2008US7391662 Semiconductor memory device with redundancy circuit
06/24/2008US7391660 Address path circuit with row redundant scheme
06/24/2008US7391659 Method for multiple step programming a memory cell
06/19/2008WO2008042598A3 Involatile memory with soft-input,soft-output (siso) decoder, statistical unit and adaptive operation
06/19/2008WO2008039692A3 Memory with cell population distribution assisted read margining
06/19/2008WO2008026204A3 Logical super block mapping for nand flash memory
06/19/2008US20080148130 Method and apparatus of cache assisted error detection and correction in memory
06/19/2008US20080148116 Method for memory cell characterization using universal structure
06/19/2008US20080148114 Redundancy programming for a memory device
06/19/2008US20080148113 Recording medium having spare area for defect management and information on defect management, and method of allocating spare area and method of managing defects
06/19/2008US20080144412 Method and device for testing memory
06/19/2008US20080144409 Byte writeable memory with bit-column voltage selection and column redundancy
06/19/2008US20080144408 Asynchronous, high-bandwidth memory component using calibrated timing elements
06/19/2008US20080144363 Method of testing pram device
06/19/2008US20080143542 Removable memory media with integral indicator light
06/19/2008US20080143406 Apparatus and method for adjusting slew rate in semiconductor memory device
06/19/2008DE102006059744A1 Halbleiter-Speicherbauelement mit redudanten Speicherzellen, und Verfahren zum Betrieb eines Halbleiter-Speicherbauelements A semiconductor memory device with memory cells redudanten, and method of operating a semiconductor memory device
06/19/2008DE102006059743A1 Halbleiter-Bauelement, insbesondere DRAM, mit mehreren einmal-programmierbaren Elementen Semiconductor component, in particular DRAM, having a plurality of one-time programmable elements
06/18/2008CN101202117A System and method for testing NVM chip
06/18/2008CN101202116A Semiconductor memory device and method for repairing the same
06/18/2008CN101202115A Method for implementing test mode of embedded non-volatility memory chip
06/18/2008CN101202109A Non-volatile semiconductor memory system and corresponding programming method
06/18/2008CN101202107A Nand flash memory device with ecc protected reserved area for non volatile storage of redundancy data
06/18/2008CN101201793A Method for distributing and testing memory
06/17/2008US7389467 Method of error correction coding, and apparatus for and method of recording data using the coding method
06/17/2008US7389459 Provision of debug via a separate ring bus in a data processing apparatus
06/17/2008US7389458 Method and apparatus for the memory self-test of embedded memories in semiconductor chips
06/17/2008US7389451 Memory redundancy with programmable control
06/17/2008US7388796 Method for testing memory under worse-than-normal conditions
06/17/2008US7388393 Semiconductor test apparatus
06/12/2008WO2008068706A1 Method and device for reconfiguration of reliability data in flash eeprom storage pages
06/12/2008WO2008068290A1 Method and semiconductor memory with a device for detecting addressing errors
06/12/2008US20080141100 Semiconductor memory device having single-level cells and multi-level cells and method of driving the semiconductor memory device
06/12/2008US20080141082 Test mode multi-byte programming with internal verify and polling function
06/12/2008US20080141081 Recording medium having spare area for defect management and information on defect management, and method of allocating spare area and method of managing defects
06/12/2008US20080141067 Memory device and method of controlling access to such a memory device
06/12/2008US20080137456 Method of testing memory device
06/12/2008US20080137455 Storage Cell Design Evaluation Circuit Including a Wordline Timing and Cell Access Detection Circuit
06/12/2008US20080137454 Semiconductor memory device and method for repairing the same
06/12/2008US20080137446 Semiconductor integrated circuit and relief method and test method of the same
06/12/2008DE102007058418A1 Fehlerkorrektur in Speicherbauteilen Error correction in memory devices
06/11/2008CN101197196A Method for detecting electrical property of flash memory unit
06/11/2008CN101197195A Data coding and decoding method and device in NOT-AND flash memory device
06/11/2008CN101197194A Memory device detecting method
06/11/2008CN101196546A Method for different IP products executing burn-in test and test board used for it
06/11/2008CN100394513C Dynamic RAM chip testing method and circuit
06/10/2008US7386851 System and method for implementing dynamic lifetime reliability extension for microprocessor architectures
06/10/2008US7386818 Efficient modeling of embedded memories in bounded memory checking
06/10/2008US7386771 Repair of memory hard failures during normal operation, using ECC and a hard fail identifier circuit
06/10/2008US7386770 Information reproduction apparatus for reproducing defect management information from defect management area sets, and an information recording apparatus for replacing defect management information
06/10/2008US7386769 On chip diagnosis block with mixed redundancy
06/10/2008US7386768 Memory channel with bit lane fail-over
06/10/2008US7386766 Address generation apparatus for turbo interleaver and deinterleaver in W-CDMA systems
06/10/2008US7386650 Memory test circuit with data expander
06/10/2008US7385863 Semiconductor memory device
06/10/2008US7385856 Non-volatile memory device and inspection method for non-volatile memory device
06/10/2008US7385835 Membrane 3D IC fabrication
06/05/2008WO2008064479A1 Circuit and method for testing multi-device systems
06/05/2008US20080134004 Recording and/or reproducing apparatus and method
06/05/2008US20080133987 Compressing test responses using a compactor
06/05/2008US20080133986 Error correction for flash memory
06/05/2008US20080133985 Semiconductor device and testing method for same
06/05/2008US20080133984 Method for Inspecting the Electrical Performance of a Flash Memory Cell
06/05/2008US20080133788 External storage subsystem
06/05/2008US20080133448 Techniques For Enhancing the Functionality of File Systems
06/05/2008US20080130387 Method for evaluating memory cell performance
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