Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
08/2007
08/09/2007US20070183214 Semiconductor device undergoing defect detection test
08/09/2007US20070182603 Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same
08/09/2007DE102006004247A1 Integrated circuit arrangement e.g. linear sensor, for analog application, has memory implementing evaluation of storage characteristic of one of memory cells based on test signal to output evaluation signal, which indicates characteristic
08/08/2007EP1816570A2 Integrated circuit I/O using a high performance bus interface
08/08/2007EP1816569A2 Integrated circuit I/O using a high performance bus interface
08/08/2007EP1815339A2 Transparent error correcting memory that supports partial-word write
08/08/2007EP1815338A2 Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
08/08/2007CN2932565Y Memory quality test device
08/08/2007CN1331379C Flash memory apparatus having single body type rotary cover
08/08/2007CN1331207C Method for evaluating semiconductor device error and system for supporting the same
08/08/2007CN1331157C Semiconductor storage device with testing and redundant function
08/08/2007CN1331156C Semiconductor storage device
08/08/2007CN101015023A Cross-point ferroelectric memory that reduces the effects of bit line to word line shorts
08/08/2007CN101015019A Apparatus and method for selectively configuring a memory device using a bi-stable relay
08/08/2007CN101014941A Memory command delay balancing in a daisy-chained memory topology
08/08/2007CN101014868A Remote bist for high speed test and redundancy calculation
08/08/2007CN101013602A Semiconductor storage device
08/07/2007US7254768 Memory command unit throttle and error recovery
08/07/2007US7254762 Semiconductor integrated circuit
08/07/2007US7254758 Method and apparatus for testing circuit units to be tested with different test mode data sets
08/07/2007US7254757 Flash memory test system and method capable of test time reduction
08/07/2007US7254756 Data compression read mode for memory testing
08/07/2007US7254754 Raid 3+3
08/07/2007US7254753 Circuit and method for configuring CAM array margin test and operation
08/07/2007US7254525 Method and apparatus for automated analysis of hard disk drive performance
08/07/2007US7254071 Flash memory devices with trimmed analog voltages
08/07/2007US7254070 Semiconductor memory device with redundancy circuit
08/07/2007US7254069 Semiconductor memory device storing redundant replacement information with small occupation area
08/07/2007US7254058 Thin film magnetic memory device provided with program element
08/07/2007US7254055 Initial firing method and phase change memory device for performing firing effectively
08/02/2007WO2007086214A1 Tester and selector
08/02/2007WO2005121961A3 Memory hub tester interface and method for use thereof
08/02/2007US20070180348 Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array
08/02/2007US20070180347 Data input method and apparatus, and liquid crystal display device using the same
08/02/2007US20070177441 Memory device having redundancy fuse blocks arranged for testing
08/02/2007US20070177440 Method for multiple step programming a memory cell
08/01/2007EP1563510B1 2t2c signal margin test mode using a defined charge exchange between bl and /bl
08/01/2007EP1450259B1 Flash memory
08/01/2007CN1329925C Semiconductor device
08/01/2007CN1329830C Methods for storing data in non-volatile memories
08/01/2007CN101009142A Method and apparatus for selectively connecting and setting each chip of semiconductor wafer
08/01/2007CN101009141A 半导体存储设备 Semiconductor memory device
07/2007
07/31/2007US7251773 Beacon to visually locate memory module
07/31/2007US7251772 Circuit arrangement having a number of integrated circuit components on a carrier substrate and method for testing a circuit arrangement of this type
07/31/2007US7251766 Test method and test circuit for electronic device
07/31/2007US7251760 Method for creating defect management information in an recording medium, and apparatus and medium based on said method
07/31/2007US7251759 Method and apparatus to compare pointers associated with asynchronous clock domains
07/31/2007US7251758 Semiconductor device testing apparatus, system, and method for testing the contacting with semiconductor devices positioned one upon the other
07/31/2007US7251757 Memory testing
07/31/2007US7251756 Method and apparatus for increasing fuse programming yield through preferred use of duplicate data
07/31/2007US7251712 Semiconductor memory device
07/31/2007US7251190 Non-volatile semiconductor memory device
07/31/2007US7251181 Techniques for storing accurate operating current values
07/31/2007US7251155 Device and method having a memory array storing each bit in multiple memory cells
07/31/2007US7250809 Boosted voltage generator
07/31/2007US7250783 Current mirror multi-channel leakage current monitor circuit and method
07/26/2007WO2007041185A3 Reconfigurable memory block redundancy to repair defective input/output lines
07/26/2007US20070174756 Reproducing circuit
07/26/2007US20070174746 Tuning core voltages of processors
07/26/2007US20070174744 Semiconductor memory device storing repair information avoiding memory cell of fail bit and operating method thereof
07/26/2007US20070174622 Protection of data of a memory associated with a microprocessor
07/26/2007US20070171759 Semiconductor memory device, system and method of testing same
07/26/2007US20070171743 Semiconductor memory device capable of writing different data in cells coupled to one word line during burn-in test
07/26/2007US20070171742 Semiconductor memory device having an open bit line structure, and method of testing the same
07/26/2007US20070171741 Method of curing analog device fail through fast transistor
07/26/2007US20070171740 Semiconductor memory module and semiconductor memory device
07/26/2007US20070171739 Semiconductor memory devices and methods of testing for failed bits of semiconductor memory devices
07/26/2007US20070171738 Semiconductor memory device
07/26/2007US20070171737 Semiconductor storage device
07/26/2007US20070171736 Method and apparatus for repairing a shorted tunnel device
07/26/2007US20070171691 Semiconductor device with electrically broken fuse and its manufacture method
07/26/2007DE102006041963A1 Halbleiter-Speicherelement A semiconductor memory element
07/25/2007EP1811525A2 Disabling faulty flash memory dies
07/25/2007EP1766632A4 System and method for testing a data storage device without revealing memory content
07/25/2007CN101006521A Test device and test method
07/25/2007CN101006520A Non-volatile semiconductor device and method for automatically correcting non-volatile semiconductor device erase operation failure
07/25/2007CN101004954A Method and apparatus for increasing yield in a memory circuit
07/25/2007CN101004953A Disabling faulty flash memory dies
07/24/2007US7249308 Algorithm to test LPAR I/O subsystem's adherence to LPAR I/O firewalls
07/24/2007US7249301 Semiconductor circuit and method for testing, monitoring and application-near setting of a semiconductor circuit
07/24/2007US7249300 Integrated circuit device including a scan test circuit and methods of testing the same
07/24/2007US7249296 Semiconductor integrated circuit
07/24/2007US7249295 Test circuit for semiconductor device
07/24/2007US7249294 Semiconductor memory device with reduced package test time
07/24/2007US7249289 Method of deciding error rate and semiconductor integrated circuit device
07/24/2007US7248524 Operating temperature optimization in a ferroelectric or electret memory
07/24/2007US7248523 Static random access memory (SRAM) with replica cells and a dummy cell
07/24/2007US7248516 Data compression read mode for memory testing
07/24/2007US7248515 Non-volatile memory with test rows for disturb detection
07/24/2007US7248514 Semiconductor memory device
07/24/2007US7248513 Semiconductor memory device having memory block configuration
07/24/2007US7248503 Semiconductor nonvolatile storage device
07/19/2007WO2007080031A1 Method and apparatus for recording high-speed input data into a matrix of memory devices
07/19/2007US20070169080 Methods and apparatus for use in updating application programs in memory of a network device
07/19/2007US20070168840 Memory block quality identification in a memory device
07/19/2007US20070168839 Interface apparatus for connecting a device and a host system, and method of controlling the interface apparatus
07/19/2007US20070168838 Reproduction apparatus and method for reproducing a unique medium identifier
07/19/2007US20070168837 Method for implementing error-correction codes in flash memory
07/19/2007US20070168836 Repair bits for a low voltage cache
07/19/2007US20070168806 Scan path circuit and semiconductor integrated circuit comprising the scan path circuit