| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
|---|
| 07/22/2008 | US7404118 Memory error analysis for determining potentially faulty memory components |
| 07/22/2008 | US7404117 Component testing and recovery |
| 07/22/2008 | US7404116 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application |
| 07/22/2008 | US7404113 Flexible row redundancy system |
| 07/22/2008 | US7404032 Configurable width buffered module having switch elements |
| 07/22/2008 | US7403436 Non-volatile semiconductor memory device |
| 07/22/2008 | US7403417 Non-volatile semiconductor memory device and method for operating a non-volatile memory device |
| 07/17/2008 | WO2008024688B1 Method, apparatus and system relating to automatic cell threshold voltage measurement |
| 07/17/2008 | WO2007136977A3 Methods and apparatus for testing delay locked loops and clock skew |
| 07/17/2008 | US20080172585 System and method for self-test of integrated circuits |
| 07/17/2008 | US20080172584 Method and system for in-place updating content stored in a storage device |
| 07/17/2008 | US20080170451 Method and circuit for setting test mode of semiconductor memory device |
| 07/17/2008 | US20080170450 Method for testing internal high voltage in nonvolatile semiconductor memory device and related voltage output circuit |
| 07/17/2008 | US20080170449 Method and Apparatus for Implementing Efuse Sense Amplifier Testing Without Blowing the Efuse |
| 07/17/2008 | US20080170448 structure for redundancy programming of a memory device |
| 07/17/2008 | US20080170445 Semiconductor memory having function to determine semiconductor low current |
| 07/17/2008 | US20080170442 Column leakage compensation in a sensing circuit |
| 07/16/2008 | EP1943529A2 Memory scan testing |
| 07/16/2008 | CN101221819A Fuse selection circuit |
| 07/16/2008 | CN100403452C Method of measuring threshold voltage for a NAND flash memory device |
| 07/16/2008 | CN100403446C Multiport scanning chain register device and method |
| 07/16/2008 | CN100403443C Method and apparatus for analyzing and repairing memory |
| 07/15/2008 | US7401281 Remote BIST high speed test and redundancy calculation |
| 07/15/2008 | US7401279 Scan path circuit and semiconductor integrated circuit comprising the scan path circuit |
| 07/15/2008 | US7401278 Edge-triggered master + LSSD slave binary latch |
| 07/15/2008 | US7401272 Apparatus and method for high speed sampling or testing of data signals using automated testing equipment |
| 07/15/2008 | US7401271 Testing system and method of using same |
| 07/15/2008 | US7401270 Repair of semiconductor memory device via external command |
| 07/15/2008 | US7401164 Methodology for performing register read/writes to two or more expanders with a common test port |
| 07/15/2008 | US7400483 Method and apparatus providing final test and trimming for a power supply controller |
| 07/15/2008 | US7400134 Integrated circuit device with multiple chips in one package |
| 07/10/2008 | WO2008083131A2 Method for programming with initial programming voltage based on trial |
| 07/10/2008 | WO2008030377A3 Defective block isolation in a non-volatile memory system |
| 07/10/2008 | WO2008018989A3 Fully- buffered dual in-line memory module with fault correction |
| 07/10/2008 | US20080168331 Memory including error correction code circuit |
| 07/10/2008 | US20080168330 Systems and methods for prioritizing error correction data |
| 07/10/2008 | US20080168328 Information recording medium to which extra ecc is applied, and method and apparatus for managing the information recording medium |
| 07/10/2008 | US20080165600 Repairing Advanced-Memory Buffer (AMB) with Redundant Memory Buffer for Repairing DRAM on a Fully-Buffered Memory-Module |
| 07/10/2008 | US20080165599 Design structure used for repairing embedded memory in an integrated circuit |
| 07/10/2008 | US20080164905 I/O interface circuit of intergrated circuit |
| 07/10/2008 | DE112006002481T5 Prüfvorrichtung, Prüfverfahren, Programm und Aufzeichnungsmedium Tester, test method, program, and recording medium |
| 07/10/2008 | DE102008003425A1 Speicherdiagnosetestschaltung und diese verwendendes Verfahren Memory Diagnostics test circuit and this method using |
| 07/10/2008 | DE102004033444B4 Integrierter Speicherschaltungsbaustein Integrated circuit memory block |
| 07/10/2008 | DE10049441B4 Verfahren zum Betrieb eines von einem Prozessor gesteuerten Systems Method for operating a system controlled by a processor |
| 07/09/2008 | EP1941368A1 Corrected data storage and handling methods |
| 07/09/2008 | EP1595211B1 Compressing test responses using a compactor |
| 07/09/2008 | CN201084430Y Chip testing device |
| 07/09/2008 | CN101217060A Systems and methods for identifying fault memory element |
| 07/09/2008 | CN100401086C Electronic circuit with test unit for testing interconnects |
| 07/09/2008 | CN100401083C Semiconductor device and method for testing the same |
| 07/08/2008 | US7398450 Parallel precoder circuit |
| 07/08/2008 | US7398448 Storage system has the function of preventing drive write error |
| 07/08/2008 | US7398439 Semiconductor device with memory and method for memory test |
| 07/08/2008 | US7397715 Semiconductor memory device for testing redundancy cells |
| 07/08/2008 | US7397714 Setting method of chip initial state |
| 07/08/2008 | US7397713 Flash EEprom system |
| 07/08/2008 | US7397709 Method and apparatus for in-system redundant array repair on integrated circuits |
| 07/08/2008 | US7397697 Multi-bit-per-cell flash EEPROM memory with refresh |
| 07/03/2008 | WO2008078529A1 Test equipment and test method |
| 07/03/2008 | WO2008077244A1 Independent link and bank selection |
| 07/03/2008 | WO2008077237A1 A program verify method for otp memories |
| 07/03/2008 | WO2008042403A3 Memory accessing circuit system |
| 07/03/2008 | US20080163163 Minimizing interaction costs among components of computer programs |
| 07/03/2008 | US20080163031 Method of facilitating reliably accessing flash memory |
| 07/03/2008 | US20080163030 Nonvolatile memory with error correction for page copy operation and method thereof |
| 07/03/2008 | US20080163029 Error correction code generation method and memory control device |
| 07/03/2008 | US20080163014 Tracking health of integrated circuit structures |
| 07/03/2008 | US20080163013 Memory testing system and method |
| 07/03/2008 | US20080159045 Semiconductor memory device capable of controlling drivability of overdriver |
| 07/03/2008 | US20080159041 Semiconductor memory and operating method of same |
| 07/03/2008 | US20080159031 Parallel read for front end compression mode |
| 07/03/2008 | US20080159030 Address pin reduction mode circuit with parallel input for semiconductor memory device and test method using the same |
| 07/03/2008 | US20080159029 Circuit for testing word line of semiconductor memory device |
| 07/03/2008 | US20080158995 Flash EEPROM System |
| 07/03/2008 | US20080158974 Apparatus with alternating read mode |
| 07/03/2008 | US20080158963 Nonvolatile memory |
| 07/03/2008 | US20080158962 Method for managing bad memory blocks in a nonvolatile-memory device, and nonvolatile-memory device implementing the management method |
| 07/03/2008 | US20080158961 Semiconductor memory device in which redundancy (rd) of adjacent column is automatically repaired |
| 07/03/2008 | US20080158960 Applying adaptive body bias to non-volatile storage |
| 07/03/2008 | DE112005000640T5 Testgerät und Testverfahren Test apparatus and test procedure |
| 07/03/2008 | DE102007058828A1 Memory element for error corection, has error examination and correction coder for producing syndrome data, which is based on information data and for display of coded data |
| 07/03/2008 | DE102007047150A1 Electronic controller for use as controller of vehicle drive machine, has microprocessor operated based on programs stored in magnetic RAM serving as non-volatile memory, and write prevent/enable device enabling write prevent function |
| 07/03/2008 | DE102006061012A1 Memory element for use in electronic system, has multiple memory cells and multiple external contact points for supplying electrical supply voltage to memory element |
| 07/02/2008 | EP1939887A1 DRAM with disabled refresh in test mode |
| 07/02/2008 | EP1540441B1 File data protection apparatus and method |
| 07/02/2008 | EP1537496B1 Data protection system and method |
| 07/02/2008 | CN101211668A Reading current structure and method for measuring static state random memorizer |
| 07/02/2008 | CN101211667A Error correction circuit and method for reducing miscorrection probability and memory device including the circuit |
| 07/02/2008 | CN101211656A Semiconductor memory device and programming method thereof |
| 07/02/2008 | CN100399527C Method and device for detecting fail bit maps of wafers |
| 07/02/2008 | CN100399475C Encoding circuit for semiconductor device and redundancy control circuit using the same |
| 07/02/2008 | CN100399473C Built-in self test system and method |
| 07/02/2008 | CN100399261C Random number generator with ring oscillation circuit |
| 07/01/2008 | US7395496 Systems and methods for enhanced stored data verification utilizing pageable pool memory |
| 07/01/2008 | US7395489 Control system and memory control method executing a detection of an error in a formation in parallel with reading operation |
| 07/01/2008 | US7395488 System and method for efficient use of memory device bandwidth |
| 07/01/2008 | US7395476 System, method and storage medium for providing a high speed test interface to a memory subsystem |
| 07/01/2008 | US7395475 Circuit and method for fuse disposing in a semiconductor memory device |
| 07/01/2008 | US7395466 Method and apparatus to adjust voltage for storage location reliability |
| 07/01/2008 | US7395465 Memory array repair where repair logic cannot operate at same operating condition as array |