Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/2007
11/27/2007US7301832 Compact column redundancy CAM architecture for concurrent read and write operations in multi-segment memory arrays
11/22/2007WO2007134253A2 Use of alternative value in cell detection
11/22/2007WO2007133963A2 Nonvolatile memory with convolutional coding for error correction
11/22/2007WO2007112201A3 Non-volatile memory and method with redundancy data buffered in data latches for defective locations
11/22/2007US20070271495 System to detect and identify errors in control information, read data and/or write data
11/22/2007US20070271494 Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices
11/22/2007US20070271485 Method and Device for Error Detection for a Cache Memory and Corresponding Cache Memory
11/22/2007US20070271045 Test apparatus and test method
11/22/2007US20070268762 Semiconductor memory and method for testing the same
11/22/2007US20070268761 Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating same
11/22/2007US20070268760 Semiconductor memory in which fuse data transfer path in memory macro is branched
11/22/2007DE102007016460A1 Nichtflüchtiges Speicherbauelement, nichtflüchtiges Speichersystem und Leseverfahren für ein nichtflüchtiges Speicherbauelement A non-volatile memory device, nonvolatile memory system and method for reading a non-volatile memory device
11/22/2007DE10156358B4 Vorrichtung und Verfahren zum Übertragen von Fehlerinformationen, die beim Testen eines Speicherbausteins für eine nachfolgende Redundanzanalyse erhalten werden, in einen Fehlerspeicher Apparatus and method for transmitting error information obtained during testing of a memory device for subsequent redundancy analysis, in a fault memory
11/21/2007EP1858028A1 Memory test engine
11/21/2007CN101075613A Semiconductor device with pad switch
11/21/2007CN101075482A Semiconductor memory and method for testing the same
11/21/2007CN100350613C Programmable memory address and decode circuits with ultra thin vertical body transistors
11/21/2007CN100350582C Method and system for observing all signals inside programmable digital IC chip
11/21/2007CN100350508C Method for testing semiconductor memory device and test circuit for semiconductor memory device
11/21/2007CN100350503C Method for reducing coupling effect between nonvolatile memory storage cell
11/20/2007US7299401 Error correction code recording method and recording apparatus using the same
11/20/2007US7299400 Error correction circuit
11/20/2007US7299388 Method and apparatus for selectively accessing and configuring individual chips of a semi-conductor wafer
11/20/2007US7299387 Address generator for block interleaving
11/20/2007US7299381 Discrete tests for weak bits
11/20/2007US7298659 Method and system for accelerated detection of weak bits in an SRAM memory device
11/20/2007US7298658 Semiconductor memory device using row redundancy and I/O redundancy scheme based on a preset order and a defect order
11/20/2007US7298657 Ferroelectric random access memory
11/20/2007US7298656 Process monitoring by comparing delays proportional to test voltages and reference voltages
11/20/2007US7297591 Method for manufacturing capacitor of semiconductor device
11/15/2007WO2007129491A1 Tester, circuit, and electronic device
11/15/2007WO2007129386A1 Test device and test method
11/15/2007WO2007112202A3 Non-volatile memory and method with redundancy data buffered in remote buffer circuits
11/15/2007WO2007103892A3 Method and apparatus for testing data steering logic for data storage having independently addressable subunits
11/15/2007WO2007103748A9 Dual-path, multimode sequential storage element
11/15/2007WO2007093172A3 Integrated circuit arrangement and method for determining the parasitic non-reactive resistance of at least the lead of at least one memory cell of an integrated circuit arrangement
11/15/2007US20070266300 Error correction device, encoder, decoder, method, and information storage device
11/15/2007US20070266299 Decoding apparatus and method therefor
11/15/2007US20070266298 Apparatus for improving data access reliability of flash memory
11/15/2007US20070266297 Controller and storage device having the same
11/15/2007US20070266296 Nonvolatile Memory with Convolutional Coding
11/15/2007US20070266295 Convolutional Coding Methods for Nonvolatile Memory
11/15/2007US20070266279 Semiconductor memory device to which test data is written
11/15/2007US20070266278 Method for at-speed testing of memory interface using scan
11/15/2007US20070266277 Memory diagnostic method
11/15/2007US20070266276 Memory block testing
11/15/2007US20070266219 Storage control apparatus capable of analyzing volume information and a control method thereof
11/15/2007US20070266201 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
11/15/2007US20070265794 Semiconductor device test apparatus and method
11/15/2007US20070263464 Independent polling for multi-page programming
11/15/2007US20070263463 Low power rom
11/15/2007US20070262800 Electronic device, circuit and test apparatus
11/15/2007DE10106775B4 Spannungsdetektionsschaltung für ein Halbleiterspeicherbauelement Voltage detection circuit for a semiconductor memory device
11/14/2007EP1083575B1 Non volatile memory with detection of short circuits between word lines
11/14/2007CN101071648A Parallel bit test circuits for testing semiconductor memory devices and related methods
11/14/2007CN101071647A Flash programmer for programming nand flash and nor/nand combined flash
11/14/2007CN101071643A Programming method for write buffer and double word flash programming
11/14/2007CN101071640A Method for verifying flash memory devices
11/14/2007CN101071633A Method and system for reducing power consumption of storage unit
11/14/2007CN101071631A Multiple banks read and data compression for back end test
11/14/2007CN101071630A Parallel read for front end compression mode
11/14/2007CN100349229C Ferroelectric memory device comprising extended memory unit
11/14/2007CN100348991C Automation inspecting method of memory body assembled state
11/14/2007CN100348982C Test method for yielding a known good die
11/13/2007US7296213 Error correction cache for flash memory
11/13/2007US7296210 Facilitating error detection for content addressable memory
11/13/2007US7296198 Method for testing semiconductor memory modules
11/13/2007US7296197 Metadata-facilitated software testing
11/13/2007US7296196 Redundant column read in a memory array
11/13/2007US7296128 Nonvolatile memory with error correction for page copy operation and method thereof
11/13/2007US7295480 Semiconductor memory repair methodology using quasi-non-volatile memory
11/13/2007US7295479 Apparatus and method for managing bad blocks in a flash memory
11/13/2007US7295469 Nonvolatile semiconductor memory device with a ROM block settable in a write/erase inhibit mode
11/08/2007WO2007125584A1 Semiconductor device and system
11/08/2007WO2007040569A3 System and method of accessing non-volatile computer memory
11/08/2007US20070260964 Semiconductor memory
11/08/2007US20070260963 Error correction system and related method thereof
11/08/2007US20070260962 Methods and apparatus for a memory device with self-healing reference bits
11/08/2007US20070260947 Measuring apparatus, measuring method, testing apparatus, testing method, and electronic device
11/08/2007US20070260946 Nonvolatile memory device comprising a programming and deletion checking option
11/08/2007US20070258299 Semiconductor memory apparatus having noise generating block and method of testing the same
11/08/2007US20070258298 Parallel programming of flash memory during in-circuit test
11/08/2007US20070258297 Method and Apparatus for Accessing Nonvolatile Memory With Read Error by Changing Read Reference
11/08/2007US20070258296 Method and apparatus for in-system redundant array repair on integrated circuits
11/08/2007US20070257716 Dft Technique for Stressing Self-Timed Semiconductor Memories to Detect Delay Faults
11/08/2007DE112005003228T5 Speicherschaltung mit einem internen Spaltenzähler für den Kompressionsprüfmodus und Verfahren zum Prüfen eines Speichers in einem Kompressionsprüfmodus A memory circuit comprising an internal column counter for the compression test and method for testing a memory in a compression test
11/08/2007DE112005003012T5 Direktzugriffsspeicher mit Prüfschaltung Random access memory with test circuit
11/08/2007DE10331543B4 Verfahren zum Testen einer zu testenden Schaltungseinheit und Schaltungsanordnung zur Durchführung des Verfahrens A method of testing a circuit under test unit and circuit arrangement for carrying out the method
11/08/2007DE10245533B4 Teststruktur zum Bestimmen eines Dotierbereiches eines Elektrodenanschlusses zwischen einem Grabenkondensator und einem Auswahltransistor in einem Speicherzellenfeld Test structure for determining a doping region of the electrode terminal between a grave capacitor and a select transistor in a memory cell array
11/08/2007DE102006018921A1 Integrierter Halbleiterspeicher mit Auffrischung von Speicherzellen Integrated semiconductor memory with refreshing of memory cells
11/08/2007DE102006007993B4 Testhilfseinrichtung in einem Speicherbaustein Test auxiliary device in a memory module
11/07/2007EP1851635A2 Enabling special modes within a digital device
11/07/2007CN101069149A Memory system with sector buffers
11/07/2007CN101067973A Fuse circuit for repair and detection of memory
11/07/2007CN101067972A Memory error-detecting and error-correcting coding circuit and method for reading and writing data utilizing the same
11/07/2007CN101067968A Apparatus and method for adaptive controlling flash storage interface reading and writing speed
11/07/2007CN101067965A Write-side calibration for data interface
11/07/2007CN100347787C Semiconductor memory with test mode and storing system using the same
11/06/2007US7293221 Methods and systems for detecting memory address transfer errors in an address bus
11/06/2007US7293220 Data accessing apparatus and method
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