Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
05/2008
05/08/2008US20080109703 Nonvolatile Memory With Modulated Error Correction Coding
05/08/2008US20080109689 Test system improving signal integrity by restraining wave reflection
05/08/2008US20080109688 Built in self test transport controller architecture
05/08/2008US20080109596 System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices
05/08/2008US20080108238 Loading a Socket and/or Adapter Device with a Semiconductor Component
05/08/2008US20080106959 Semiconductor memory device having advanced test mode
05/08/2008US20080106958 Semiconductor chip package and method and system for testing the same
05/08/2008US20080106957 Method and apparatus for generating high-frequency command and address signals for high-speed semiconductor memory device testing
05/08/2008US20080106956 Sram Test Method and Sram Test Arrangement to Detect Weak Cells
05/08/2008US20080106939 Storage device employing a flash memory
05/08/2008DE102006052329A1 Data memory system i.e. mass memory system, for electronic system, has controller e.g. microprocessor, setting status indicator, which indicates whether current interruption is depressed while writing data-entity into flash-memory
05/08/2008DE102006051135A1 Connection quality test method, involves comparing reflected signals, which are produced in reaction to test signal or generated signals, with two threshold values, where one value differs from other value
05/07/2008EP1918939A1 Semiconductor memory system for flash memory
05/07/2008CN101174474A Fault detection method for grids flash memory separation
05/07/2008CN101174473A Method of providing block state information in semiconductor memory device including flash memory
05/07/2008CN101174472A Screening method for defected memory cell
05/07/2008CN101173969A System, device and method for implementing complete automatic test of MP3 player
05/07/2008CN100387001C System of virtual cascade time delay alignment characteristic used for testing chip and its method
05/07/2008CN100386822C Method for testing a memory device
05/07/2008CN100386744C Method and system for secure erasure of information in non-volatile memory in an electronic device
05/06/2008US7370261 Convolution-encoded raid with trellis-decode-rebuild
05/06/2008US7370260 MRAM having error correction code circuitry and method therefor
05/06/2008US7370254 Compressing test responses using a compactor
05/06/2008US7370251 Method and circuit for collecting memory failure information
05/06/2008US7370250 Test patterns to insure read signal integrity for high speed DDR DRAM
05/06/2008US7370249 Method and apparatus for testing a memory array
05/06/2008US7370248 In-service raid mirror reconfiguring
05/06/2008US7370237 Semiconductor memory device capable of accessing all memory cells
05/06/2008US7370168 Memory card conforming to a multiple operation standards
05/06/2008US7370151 Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache
05/06/2008US7369455 Calibration circuit of a semiconductor memory device and method of operating the same
05/02/2008WO2008050527A1 Semiconductor testing apparatus and method of testing semiconductor memory
05/02/2008WO2008049719A1 Test method for computer system-assisted devices with at least one memory area
05/01/2008US20080104484 Mass storage system and method
05/01/2008US20080104473 Rendering and correcting data
05/01/2008US20080104466 Method and Apparatus for Testing Embedded Cores
05/01/2008US20080104460 Medium defect detector and information reproducing device
05/01/2008US20080101142 Semiconductor memory device and method of testing same
05/01/2008US20080101141 Method of arranging fuses in a fuse box of a semiconductor memory device and a semiconductor memory device including such an arrangement
05/01/2008US20080100424 Semiconductor Apparatus and Method of Testing Semiconductor Apparatus
04/2008
04/30/2008DE60221836T2 Verfahren und vorrichtung zur optimierten parallelen prüfung und zum zugriff auf elektronische schaltung Method and apparatus for optimizing parallel testing and access to electronic circuit
04/30/2008DE102007015915A1 Computer system-assisted electronic data processing device testing method, involves continuously writing data in unused portion of passive storage area, and comparing data with reference data to conclude functional capability of memories
04/30/2008DE102006051591B3 Memory chip i.e. dynamic RAM memory chip, testing method, involves determining that all data outputs of memory chips lie close to logical zero and one, if signal level at input falls below and exceeds threshold level, respectively
04/30/2008DE10106775B9 Spannungsdetektionsschaltung für ein Halbleiterspeicherbauelement Voltage detection circuit for a semiconductor memory device
04/30/2008CN101171644A Method and apparatus for transmitting data
04/30/2008CN101169975A Memory test method
04/30/2008CN100385638C Test sample for bridging and continuous testing
04/30/2008CN100385568C Memory element, method of repairing its defect memory unit automatically and method of its access
04/29/2008USRE40282 Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device
04/29/2008US7366970 Method and test device for detecting addressing errors in control units
04/29/2008US7366967 Methods of testing semiconductor memory devices in a variable CAS latency environment and related semiconductor test devices
04/29/2008US7366966 System and method for varying test signal durations and assert times for testing memory devices
04/29/2008US7366965 Semiconductor integrated circuit
04/29/2008US7366962 Interleaving/deinterleaving method and apparatus
04/29/2008US7366947 High reliability memory module with a fault tolerant address and command bus
04/29/2008US7366946 ROM redundancy in ROM embedded DRAM
04/29/2008US7366597 Validating control system software variables
04/29/2008US7366042 Defective column(s) in a memory device/card is/are skipped while serial data programming is performed
04/29/2008US7366034 Nonvolatile memory
04/29/2008US7365555 Semiconductor device, method for testing the same and IC card
04/29/2008US7365554 Integrated circuit for determining a voltage
04/24/2008WO2008048944A2 Using sam in error correcting code encoder and decoder implementations
04/24/2008WO2008023334A3 Method for testing a static random access memory
04/24/2008US20080098282 High speed error correcting system
04/24/2008US20080098281 Using sam in error correcting code encoder and decoder implementations
04/24/2008US20080098280 N-dimensional iterative ECC method and apparatus with combined erasure - error information and re-read
04/24/2008US20080098278 Multiplier product generation based on encoded data from addressable location
04/24/2008US20080098265 System and Method for Embedded Java Memory Footprint Performance Improvement
04/24/2008US20080098253 Method of timing calibration using slower data rate pattern
04/24/2008US20080098050 Defect Management for Storage Media
04/24/2008US20080094932 Semiconductor memory device and methods thereof
04/24/2008US20080094926 Portable device for storing private information such as medical, financial or emergency information
04/24/2008US20080094924 Memory device having selectively decoupleable memory portions and method thereof
04/24/2008US20080094899 Non-volatile semiconductor memory device
04/24/2008US20080094891 Parallel Threshold Voltage Margin Search for MLC Memory Application
04/24/2008US20080094869 Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to NWELLS and PWELLS
04/24/2008US20080094640 Methods and systems for precisely relatively positioning a waist of a pulsed laser beam and method for controlling energy delivered to a target structure
04/24/2008DE10204409B4 Verfahren zum Speichern von Daten in einer Speichereinrichtung mit Zugriffsmöglichkeit auf redundante Speicherzellen A method for storing data in a memory device with the possibility of accessing redundant memory cells
04/24/2008DE102006044530A1 Vorrichtung und Verfahren zur Strommessung bzw. Stromverstärkung Apparatus and method for power measurement or current gain
04/23/2008EP1914757A2 Storage device and storing method
04/23/2008EP1914752A1 High-speed error correcting apparatus with efficient data transfer
04/23/2008EP1665285B1 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
04/23/2008CN101167141A Test system for storage chip in MCP or SIP
04/23/2008CN101167140A Memory having a portion that can be switched between use as data and use as error correction code (ECC)
04/23/2008CN101165808A Semiconductor device and test system which output fuse cut information sequentially
04/23/2008CN101165495A Method and apparatus for increasing clock frequency and data rate for semiconductor devices
04/23/2008CN100383892C Memory device having page buffer with double-register and its using method
04/23/2008CN100383887C Data recording/reproducing system, data recording/reproducing method
04/23/2008CN100383886C Error correcting device and method
04/22/2008US7363565 Method of testing apparatus having master logic unit and slave logic unit
04/22/2008US7363558 Semiconductor device and method for testing the same
04/22/2008US7363556 Testing apparatus and testing method
04/22/2008US7363555 Memory cell test circuit for use in semiconductor memory device and its method
04/22/2008US7363554 Method of detecting errors in a priority encoder and a content addressable memory adopting the same
04/22/2008US7363552 Method and apparatus for convolutional interleaving/de-interleaving technique
04/22/2008US7363533 High reliability memory module with a fault tolerant address and command bus
04/22/2008US7363422 Configurable width buffered module
04/22/2008US7362652 Semiconductor circuit
04/22/2008US7362633 Parallel read for front end compression mode
04/22/2008US7362632 Test parallelism increase by tester controllable switching of chip select groups
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