Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
09/2007
09/04/2007US7266735 Semiconductor device having ECC circuit
09/04/2007US7266732 MRAM with controller
09/04/2007US7266675 Processor including a register file and method for computing flush masks in a multi-threaded processing system
09/04/2007US7266666 Method for fast verification of sector addresses
09/04/2007US7266634 Configurable width buffered module having flyby elements
09/04/2007US7266036 Semiconductor memory device
09/04/2007US7266025 Semiconductor integrated circuit
09/04/2007US7266017 Method for selective erasing and parallel programming/verifying of cell blocks in a flash EEprom system
09/04/2007US7266009 Ferroelectric memory
09/04/2007US7265568 Semi-conductor component test process and a system for testing semi-conductor components
08/2007
08/30/2007WO2007095974A1 Testing non-volatile memory devices for charge leakage
08/30/2007WO2007078830A3 Repair bits for low voltage cache
08/30/2007US20070204208 Device and method for correcting kinescope scan distortion
08/30/2007US20070204203 Layered multiple description coding
08/30/2007US20070204202 Information recording disc, recording and/or reproducing device and method
08/30/2007US20070204201 High reliability memory module with a fault tolerant address and command bus
08/30/2007US20070204200 High reliability memory module with a fault tolerant address and command bus
08/30/2007US20070204199 Semiconductor memory device and memory system including the same
08/30/2007US20070204190 Test algorithm selection in memory built-in self test controller
08/30/2007US20070204189 Method and system for testing a random access memory (RAM) device having an internal cache
08/30/2007US20070201293 Testing method for permanent electrical removal of an integrated circuit output
08/30/2007US20070201289 Embedded memory and methods thereof
08/30/2007US20070200544 Method and apparatus providing final test and trimming for a power supply controller
08/30/2007DE112005002581T5 Testvorrichtung und Testverfahren Test apparatus and test procedure
08/30/2007DE102006031038A1 Memory arrangement for computer systems, has testing device, for processing data in form of data packets, and is connected with port of interface and activates memory bank access device
08/30/2007DE102006009224A1 Integrated circuit chip, comprising chip-internal memory and test circuit, which is designed to implement functional test of chip-internal memory
08/30/2007DE102006008017A1 Production method for producing integrated semiconductor, involves installing integrated semiconductor memory, which has multiple state with memory cell field and memory cell for storage of data value and storage circuit for storage of data
08/29/2007EP1825479A2 Programmable memory built-in-self-test (mbist) method and apparatus
08/29/2007CN101026156A 半导体器件 Semiconductor devices
08/29/2007CN100334565C Data management apparatus and method of flash memory
08/29/2007CN100334558C Method for monitoring simulation chip internal EEPROM
08/28/2007US7263650 Error correction extending over multiple sectors of data storage
08/28/2007US7263648 Apparatus and method for accommodating loss of signal
08/28/2007US7263646 Method and apparatus for skew compensation
08/28/2007US7263633 Integrated circuit, in particular integrated memory, and methods for operating an integrated circuit
08/28/2007US7263591 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
08/28/2007US7263455 Apparatus and methods for ferroelectric ram fatigue testing
08/28/2007US7263010 Semiconductor memory device with test circuit
08/28/2007US7262479 Layout structure of fuse bank of semiconductor memory device
08/23/2007US20070198894 Information recording disc, recording and/or reproducing device and method
08/23/2007US20070198893 Error correction block, method and apparatus for generating error correction block, and error correction method
08/23/2007US20070198892 Systems And Methods For Detecting A Failure Event In A Field Programmable Gate Array
08/23/2007US20070198885 Semiconductor integrated circuit and test system for testing the same
08/23/2007US20070198880 Semiconductor integrated circuit and testing method thereof
08/23/2007US20070195638 Delay-locked loop, integrated circuit having the same, and method of driving the same
08/23/2007US20070195623 Apparatus and method for dynamically repairing a semiconductor memory
08/23/2007US20070195622 Semiconductor memory device with redundancy circuit
08/23/2007US20070195621 Method and apparatus for increasing yield in a memory circuit
08/23/2007US20070195620 Semiconductor memory
08/23/2007US20070195619 Integrated circuit memory devices having multi-bit normal memory cells and single-bit redundant memory cells therein
08/23/2007US20070195618 Memory device fail summary data reduction for improved redundancy analysis
08/23/2007US20070195575 Semiconductor integrated circuit
08/23/2007US20070195573 Dynamic ram-and semiconductor device
08/23/2007DE102006006546A1 Memory chip comprises multiple memory cells, programmable selecting device, irreversible programmable hardware programming unit, which releases fuse signal, decoding device and evasion circuit
08/22/2007CN101022039A Apparatus and method for identifying synchronous memory controller based on field programmable gate array
08/21/2007US7260757 System and method for testing electronic devices on a microchip
08/21/2007US7260754 Semiconductor device with speed binning test circuit and test method thereof
08/21/2007US7260020 Synchronous global controller for enhanced pipelining
08/21/2007US7260016 Non-volatile semiconductor memory device and writing method therefor
08/21/2007US7260012 Fuse latch circuit
08/21/2007US7260004 Method and apparatus for increasing yield in a memory circuit
08/21/2007US7259595 Circuit and method for detecting frequency of clock signal and latency signal generation circuit of semiconductor memory device with the circuit
08/16/2007US20070192665 System with read protecting function
08/16/2007US20070192664 Semiconductor memory
08/16/2007US20070192657 Configuring flash memory
08/16/2007US20070192656 Error detection device and method for error detection for a command decoder
08/16/2007US20070190722 Method to form upward pointing p-i-n diodes having large and uniform current
08/16/2007US20070189088 Semiconductor integrated circuit and testing method therefor
08/16/2007US20070189079 Memory device with page buffer having dual registers and method of using the same
08/16/2007US20070189054 Setting method of chip initial state
08/16/2007DE102006053281A1 Halbleiterbauelement, Testsystem und ODT-Testverfahren A semiconductor device test system and test method ODT
08/15/2007EP1402278B1 Method and apparatus for optimized parallel testing and access of electronic circuits
08/15/2007EP1332500B1 Writable tracking cells
08/15/2007EP1030314B1 Device and method for testing a non-volatile reprogrammable memory
08/15/2007CN1332394C Multifunctional serial entry/output circuit
08/15/2007CN101019326A File download and streaming system
08/15/2007CN101019192A Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations
08/14/2007US7257763 Content addressable memory with error signaling
08/14/2007US7257762 Memory interface with write buffer and encoder
08/14/2007US7257761 Method for preventing read errors in optical disc drive
08/14/2007US7257754 Semiconductor memory device and test pattern data generating method using the same
08/14/2007US7257753 Semiconductor testing apparatus
08/14/2007US7257751 Apparatus and method for random pattern built in self-test
08/14/2007US7257749 Probeless testing of pad buffers on wafer
08/14/2007US7257747 Apparatus for testing USB memory and method thereof
08/14/2007US7257745 Array self repair using built-in self test techniques
08/14/2007US7257733 Memory repair circuit and method
08/14/2007US7257667 Status register to improve initialization of a synchronous memory
08/14/2007US7257666 Method of writing, erasing, and controlling memory for memory device
08/14/2007US7257664 Adaptive error resilience for signal transmission over a network
08/14/2007US7257039 Bit line discharge control method and circuit for a semiconductor memory
08/14/2007US7257020 Thin film magnetic memory device having redundant configuration
08/14/2007US7256594 Method and apparatus for testing semiconductor devices using the back side of a circuit board
08/09/2007US20070186141 Method and information apparatus for improving data reliability
08/09/2007US20070183233 Semiconductor integrated circuit device
08/09/2007US20070183232 Semiconductor memory device
08/09/2007US20070183231 Method of operating a memory system
08/09/2007US20070183230 Memory redundance circuit techniques
08/09/2007US20070183229 Multi chip package and related method
08/09/2007US20070183228 Control signal interface circuit for computer memory modules
1 ... 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 ... 306