Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
10/2007
10/18/2007DE102006062023A1 Testbetrieb einer Multiport-Speichervorrichtung Test operation of a multi-port memory device
10/18/2007DE102006017546A1 Verfahren und System zum Testen einer Speichervorrichtung A method and system for testing a memory device
10/18/2007DE102006016499A1 Memory device`s error correction method, involves selecting and checking data blocks for errors in order to detect defective data blocks, and determining bits of defective data blocks and redundant information during existence of error
10/17/2007EP1417502B1 Electronic circuit and method for testing
10/17/2007EP1221165B1 Circuit and method for a multiplexed redundancy scheme in a memory device
10/17/2007CN101055768A 半导体存储装置 The semiconductor memory device
10/17/2007CN101055767A Test operation of multi-port memory device
10/17/2007CN101055762A Semiconductor storage device, and control method and test method of semiconductor storage device
10/17/2007CN101055761A Semiconductor storage device, and control method and test method of semiconductor storage device
10/17/2007CN100343991C Repair fuse box of semiconductor device
10/17/2007CN100343923C Method of testing SDRAM device
10/17/2007CN100343769C Programmable fuse array circuit and method for disposable terminal user
10/16/2007US7284169 System and method for testing write strobe timing margins in memory devices
10/16/2007US7284168 Method and system for testing RAM redundant integrated circuits
10/16/2007US7284167 Automated tests for built-in self test
10/16/2007US7284166 Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays
10/16/2007US7284134 ID installable LSI, secret key installation method, LSI test method, and LSI development method
10/16/2007US7283409 Data monitoring for single event upset in a programmable logic device
10/16/2007US7283397 Flash EEprom system capable of selective erasing and parallel programming/verifying memory cell blocks
10/16/2007US7283385 RRAM communication system
10/11/2007WO2007114933A2 Rotatable pedestal
10/11/2007US20070240021 Method, system and program product for autonomous error recovery for memory devices
10/11/2007US20070237011 NAND string with a redundant memory cell
10/11/2007US20070237009 Methods and apparatus for improved memory access
10/11/2007DE112005002390T5 Burst-Betrieb für die Speichertransaktion und Speicherkomponenten, welche die zeitweilig multiplexierte Fehlerkorrekturcodierung unterstützen A burst mode for the memory transaction and storage components which support the temporarily multiplexed error correction coding
10/11/2007DE10297097B4 Schmelzprogrammierbare E/A-Organisation Melting Programmable I / O organization
10/11/2007DE102007013317A1 Paralleles Lesen für Eingangskomprimierungsmodus Parallel reading for input compression mode
10/11/2007DE102007013316A1 Mehrbanklesen und Datenkomprimierung für Ausgangstests More Banking reading and data compression for initial tests
10/11/2007DE102007010310A1 Eingabeschaltung eines Halbleiterspeicherelements, Halbleiterspeicherelement und Verfahren zum Steuern der Eingabeschaltung Input circuit of a semiconductor memory element, semiconductor memory device and method for controlling the input circuit
10/10/2007EP1563510B8 2t2c signal margin test mode using a defined charge exchange between bl and /bl
10/10/2007CN101051525A Semiconductor storage device, and control method and test method of semiconductor storage device
10/10/2007CN100342457C Duty-cycle-efficent SRAM cell test
10/10/2007CN100342455C Semiconductor storage and method for testing same
10/10/2007CN100342240C Method for testing dynamic memory circuit and testing circuit
10/09/2007US7281180 Memory system and test method therefor
10/09/2007US7281179 Memory device and input signal control method of a memory device
10/09/2007US7281178 System and method for write-enable bypass testing in an electronic circuit
10/09/2007US7281177 Autonomic parity exchange
10/09/2007US7281155 Semiconductor memory device and method for executing shift redundancy operation
10/09/2007US7280420 Data compression read mode for memory testing
10/09/2007US7279918 Methods for wafer level burn-in
10/04/2007WO2007112202A2 Non-volatile memory and method with redundancy data buffered in remote buffer circuits
10/04/2007WO2007112201A2 Non-volatile memory and method with redundancy data buffered in data latches for defective locations
10/04/2007WO2007112163A2 Error correction device and methods thereof
10/04/2007WO2007110927A1 Semiconductor memory
10/04/2007WO2007110926A1 Semiconductor memory and test system
10/04/2007WO2007110327A1 Method for operating a memory unit
10/04/2007WO2007110325A1 Method for operating a memory unit comprising the marking of memory blocks that are identified as defective
10/04/2007WO2007109876A1 Power supply testing architecture
10/04/2007US20070234183 Multi-bit memory device and memory system
10/04/2007US20070234182 Error checking and correction (ECC) system and method
10/04/2007US20070234181 Error correction device and methods thereof
10/04/2007US20070234155 Probeless testing of pad buffers on wafer
10/04/2007US20070234144 Smart Verify For Multi-State Memories
10/04/2007US20070234143 Semiconductor memory devices and methods of testing for failed bits of semiconductor memory devices
10/04/2007US20070234142 Memory system, memory system controller, and a data processing method in a host apparatus
10/04/2007US20070234141 Concept For Testing An Integrated Circuit
10/04/2007US20070234140 Method and apparatus for determining relative relevance between portions of large electronic documents
10/04/2007US20070234138 Semiconductor integrated circuit and method for testing semiconductor integrated circuit
10/04/2007US20070234137 Semiconductor integrated circuit and method of production of same
10/04/2007US20070234120 Semiconductor storage device
10/04/2007US20070230261 Nonvolatile semiconductor memory device and method for testing the same
10/04/2007US20070230260 Automatic shutdown or throttling of a bist state machine using thermal feedback
10/04/2007US20070230246 Non-volatile semiconductor memory device
10/04/2007US20070230245 Semiconductor Storage Device
10/04/2007DE69936277T2 Synchron-Halbleiterspeichervorrichtung Synchronous semiconductor memory device
10/04/2007DE69636805T2 Massenspeicherplattenanordnung zur Verwendung in Rechnersystemen Mass storage disk array for use in computer systems
10/04/2007DE102007011091A1 Semiconductor memory e.g. synchronous dynamic random access memory, testing method, involves activating output circuit in reaction to activated data output clock signal, and serializing test data transmitted through activated circuit
10/03/2007EP1665287B8 Management of defective blocks in flash memories
10/03/2007CN101047021A Method for calibration of memory devices, and apparatus thereof
10/02/2007US7278085 Simple error-correction codes for data buffers
10/02/2007US7278078 Built-in self-test arrangement for integrated circuit memory devices
10/02/2007US7278072 Method and auxiliary device for testing a RAM memory circuit
10/02/2007US7278060 System and method for on-board diagnostics of memory modules
10/02/2007US7277981 Scratch control memory array in a flash memory device
10/02/2007US7277338 Method and device for testing semiconductor memory devices
10/02/2007US7277337 Memory module with a defective memory chip having defective blocks disabled by non-multiplexed address lines to the defective chip
10/02/2007US7277330 Nonvolatile semiconductor memory device having improved redundancy relieving rate
10/02/2007US7277311 Flash cell fuse circuit
10/02/2007US7277306 Associative memory capable of searching for data while keeping high data reliability
10/02/2007US7277011 Removable memory media with integral indicator light
10/02/2007US7276930 Circuit and method for detecting skew of transistor in semiconductor device
09/2007
09/27/2007WO2007108400A1 Testing apparatus, memory device and testing method
09/27/2007WO2007107182A1 Adjusting a digital delay function of a data memory unit
09/27/2007US20070226603 Method and system for indicating an executable as trojan horse
09/27/2007US20070226593 Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously
09/27/2007US20070226592 Variable sector-count ECC
09/27/2007US20070226591 Integrated device for simplified parallel testing, test board for testing a plurality of integrated devices, and test system and tester unit
09/27/2007US20070226590 Semiconductor memory in which error correction is performed by on-chip error correction circuit
09/27/2007US20070226589 System and method for error correction in cache units
09/27/2007US20070226553 Multiple banks read and data compression for back end test
09/27/2007US20070226552 Semiconductor integrated circuit and the same checking method
09/27/2007US20070226234 Recording medium with status information thereon which changes upon reformatting and apparatus and methods for forming, recording, and reproducing the recording medium
09/27/2007US20070223293 Parallel read for front end compression mode
09/27/2007US20070223292 Method for column redundancy using data latches in solid-state memories
09/27/2007US20070223291 Method for remote redundancy for non-volatile memory
09/27/2007US20070223277 Flash memory
09/27/2007US20070223266 One-time-programmable (OTP) memory device and method for testing the same
09/27/2007DE112004000676T5 Prüfvorrichtung Tester
09/27/2007DE10153753B4 Speichertester unterläßt ein Programmieren von Adressen in erfaßten schlechten Spalten Memory tester fails, programming of addresses in the detected bad columns
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