Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
12/2008
12/31/2008CN100448011C Antifuse programming circuit in which one stage of transistor is interposed in a series with antifuse between power supplies during programming
12/31/2008CN100447897C Semiconductor storage and its testing method
12/30/2008US7472332 Method for the reliability of host data stored on fibre channel attached storage subsystems
12/30/2008US7472331 Memory systems including defective block management and related methods
12/30/2008US7472330 Magnetic memory which compares compressed fault maps
12/30/2008US7472326 Semiconductor test system having multitasking algorithmic pattern generator
12/30/2008US7472325 Method for segmenting BIST functionality in an embedded memory array into remote lower-speed executable instructions and local higher-speed executable instructions
12/30/2008US7471585 Semiconductor memory
12/30/2008CA2447882C Robust bit scheme for a memory of a replaceable printer component
12/25/2008US20080320368 Error Detection and Correction Circuit and Semiconductor Memory
12/25/2008US20080320367 Apparatus for accessing and transferring optical data
12/25/2008US20080320366 Methods of reading nonvolatile memory
12/25/2008US20080320347 Testing of Integrated Circuits Using Test Module
12/25/2008US20080320346 Systems for reading nonvolatile memory
12/25/2008US20080316846 Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device
12/25/2008US20080316845 Memory row architecture having memory row redundancy repair function
12/25/2008US20080316838 Redundancy memory cell access circuit and semiconductor memory device including the same
12/24/2008WO2008155678A1 Detection of defective data sequences
12/24/2008EP2006859A2 Semiconductor memory
12/24/2008EP2005440A1 Method for operating a memory unit
12/24/2008EP2005203A1 Power supply testing architecture
12/24/2008DE10256487B4 Integrierter Speicher und Verfahren zum Testen eines integrierten Speichers Integrated memory and method for testing an integrated memory
12/24/2008DE10063626B4 Verfahren zum Testen der Leistungsfähigkeit einer DRAM-Vorrichtung A method for testing the performance of a DRAM device
12/24/2008CN101331554A Memory with retargetable memory cell redundancy
12/24/2008CN101329918A Built-in self-repairing system and method for memory
12/24/2008CN101329917A Method for repairing defect of DRAM
12/24/2008CN101329916A Flash memory device error correction code controllers and related methods and memory systems
12/24/2008CN100446129C Method and system for RAM fault testing
12/24/2008CN100446128C ROM circuit capable of debugging and updating and method of debugging and updating
12/23/2008US7469369 Low power content-addressable-memory device
12/23/2008US7469368 Method and system for a non-volatile memory with multiple bits error correction and detection for improving production yield
12/23/2008US7469360 Method and apparatus for testing a memory device
12/23/2008US7468922 Apparatus and method for dynamically repairing a semiconductor memory
12/23/2008US7468623 Clamp circuit with fuse options
12/18/2008WO2008154290A1 Memory repair system and method
12/18/2008WO2008152728A1 Error correcting method and computing element
12/18/2008WO2008152694A1 Tester
12/18/2008US20080313511 System-in-package and method of testing thereof
12/18/2008US20080313510 Systems and devices including memory with built-in self test and methods of making and using the same
12/18/2008US20080313249 Random number generator with ring oscillation circuit
12/18/2008US20080312863 System and method for implementing a programmable dma master with date checking utilizing a drone system controller
12/18/2008DE10124112B4 Halbleiterspeicher für Hochgeschwindigkeitsbetrieb und Verfahren zum Antreiben einer Wortleitung A semiconductor memory for high speed operation and method of driving a word line
12/17/2008EP2003653A1 Test device and test method
12/17/2008EP2003652A2 Semiconductor memory and test system
12/17/2008EP2002447A2 Non-volatile memory and method with redundancy data buffered in remote buffer circuits
12/17/2008EP2002446A1 Method for operating a memory unit comprising the marking of memory blocks that are identified as defective
12/17/2008EP1875477A4 Memory having a portion that can be switched between use as data and use as error correction code (ecc)
12/17/2008CN101325090A Offsetting cyclic redundancy code lanes from data lanes to reduce latency
12/17/2008CN100444409C Silicon plate, method for producing silicon plate and solar cell
12/17/2008CN100444287C Time controllable sensing project for sensing amplifier in storage test
12/17/2008CN100444286C Memory cell signal window testing apparatus
12/17/2008CN100444122C Memory arrangement in a computer system
12/16/2008US7467339 Semiconductor integrated circuit and a method of testing the same
12/16/2008US7467334 Method for repairing a semiconductor memory
12/16/2008US7467323 Data processing system and method for efficient storage of metadata in a system memory
12/16/2008US7466160 Shared memory bus architecture for system with processor and memory units
12/11/2008WO2008005184A3 Improvements in or relating to the copy protection of optical discs
12/11/2008US20080307278 Apparatus for efficiently loading scan and non-scan memory elements
12/11/2008US20080307276 Memory Controller with Loopback Test Interface
12/11/2008US20080307274 Memory apparatus and method and reduced pin count apparatus and method
12/11/2008US20080307260 Semiconductor ic incorporating a co-debugging function and test system
12/11/2008US20080304345 Semiconductor memory device with reduced number of channels for test operation
12/11/2008US20080304344 Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device
12/11/2008US20080304343 Method and apparatus for testing a circuit
12/11/2008US20080304342 Semiconductor memory device with redundancy ciruit
12/11/2008US20080304332 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
12/11/2008US20080304331 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
12/11/2008US20080304327 Methods and apparatuses for refreshing non-volatile memory
12/11/2008US20080302559 Flexible and elastic dielectric integrated circuit
12/11/2008DE112006002842T5 Speicher-Diagnose-Vorrichtung Memory diagnosis device
12/10/2008EP1999593A2 Firmware extendable commands for a microcontroller based flash memory digital controller
12/10/2008EP1886155A4 Memory device and method having a data bypass path to allow rapid testing and calibration
12/10/2008EP1089293B1 Memory test method and nonvolatile memory with low error masking probability
12/10/2008CN201163539Y Electric property tester for internal memory
12/10/2008CN101322317A Apparatus and method for channel interleaving in communications system
12/10/2008CN101320596A Bad block management method facing high-capacity FLASH solid memory
12/10/2008CN101320592A High-capacity FLASH solid memory controller
12/10/2008CN100442434C Semiconductor memory having segmented row repair
12/10/2008CN100442396C Apparatus and method for testing semiconductor memory devices
12/10/2008CN100442395C Integrated circuit with self-test device for embedded non-volatile memory and related test method
12/10/2008CN100442386C Semiconductor memory device
12/10/2008CN100442383C Semiconductor integrated circuit device and error detecting method therefor
12/10/2008CN100442241C Soft error correction method, memory control apparatus and memory system
12/09/2008US7464322 System and method for detecting write errors in a storage device
12/09/2008US7464321 Apparatus and method to transfer information from a first information storage and retrieval system to a second information storage and retrieval system
12/09/2008US7464320 Synchronous semiconductor storage device having error correction function
12/09/2008US7464309 Method and apparatus for testing semiconductor memory device and related testing methods
12/09/2008US7464308 CAM expected address search testmode
12/09/2008US7464306 Status of overall health of nonvolatile memory
12/09/2008US7464241 Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding
12/09/2008US7463548 Method for performing a burn-in test
12/09/2008US7463508 SRAM test method and SRAM test arrangement to detect weak cells
12/04/2008WO2008146393A1 Memory testing method, memory testing device and dram
12/04/2008WO2008055099A3 Memory bus output driver of a multi-bank memory device and method therefor
12/04/2008WO2007103590A3 Error correction device and method thereof
12/04/2008US20080301531 Fault tolerant encoding of directory states for stuck bits
12/04/2008US20080301530 Apparatus and method for distinguishing temporary and permanent errors in memory modules
12/04/2008US20080301529 Apparatus and method for distinguishing single bit errors in memory modules
12/04/2008US20080301528 Method and apparatus for controlling memory
12/04/2008US20080301526 Memory Device with Error Correction Capability and Preemptive Partial Word Write Operation
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