Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
10/2008
10/23/2008US20080259702 State-monitoring memory element
10/23/2008US20080259701 Redundancy architecture for an integrated circuit memory
10/23/2008US20080259697 Semiconductor memory device having output impedance adjustment circuit and test method of output impedance
10/23/2008US20080259695 Semiconductor Memory Devices Having a Demultiplexer and Related Methods of Testing Such Semiconductor Memory Devices
10/23/2008DE69937559T2 Nicht-flüchtige Speicher mit Erkennung von Kurzschlüssen zwischen Wortleitungen Non-volatile memory with detection of shorts between word lines
10/23/2008DE102008013099A1 Speichertestschaltung Memory test circuit
10/23/2008DE102007033031A1 Integrierte Schaltung, Speichermodul, Verfahren zum Betreiben einer integrierten Schaltung, Verfahren zum Herstellen einer integrierten Schaltung, Computerprogramm sowie Computersystem Integrated circuit, memory, the method of operating an integrated circuit, A method for fabricating an integrated circuit, computer program and computer system
10/23/2008DE102007017735A1 Speichervorrichtung und Vorrichtung zum Auslesen Storage device, and means for reading out
10/23/2008DE10164032B4 Verfahren zum Aktivieren von Sicherungseinheiten in elektronischen Schaltungseinrichtungen Method for activating fuse units in electronic circuitry
10/22/2008EP1982264A2 Method for estimating and reporting the life expectancy of flash-disk memory
10/22/2008CN101290807A Simulating method of circuit stability of static random access memory
10/22/2008CN101290806A Semiconductor memory device
10/22/2008CN101290805A Semiconductor device and data processing system
10/22/2008CN101290804A Analyzer with built-in backup element and analysis method of backup element
10/22/2008CN101290566A Random number generator with ring oscillation circuit
10/22/2008CN100428364C Testing method of memory address line
10/22/2008CN100428187C Nonvolatile memory apparatus
10/22/2008CN100428175C Method for inspecting fault code in data
10/21/2008US7441167 Memory module with parallel testing
10/21/2008US7441166 Testing apparatus and testing method
10/21/2008US7441165 Read-only memory and operational control method thereof
10/21/2008US7441164 Memory bypass with support for path delay test
10/21/2008US7441156 Semiconductor memory device having advanced test mode
10/21/2008US7441090 System and method for updating data sectors in a non-volatile memory using logical block addressing
10/21/2008US7440884 Memory rewind and reconstruction for hardware emulator
10/21/2008US7440348 Memory array having a redundant memory element
10/21/2008US7440347 Circuit and method to find wordline-bitline shorts in a DRAM
10/21/2008US7440346 Semiconductor device
10/21/2008US7440337 Nonvolatile semiconductor memory apparatus having buffer memory for storing a program and buffering work data
10/16/2008WO2008124095A1 Serial interface memory testing apparatus and method
10/16/2008US20080256420 Error checking addressable blocks in storage
10/16/2008US20080256416 Apparatus and method for initializing memory
10/16/2008US20080253215 Semiconductor memory circuit
10/16/2008US20080253209 Semiconductor memory device and method of testing same
10/16/2008US20080253208 Semiconductor integrated circuit and memory checking method
10/16/2008DE112004002615B4 Verfahren zur Kalibrierung eines Zeitsteuertakts A method for calibrating a timing clock
10/16/2008DE102004003357B4 Dynamische, in FeRAMS integrierte Referenzspannungskalibrierung Dynamic, integrated in FeRAMS reference voltage calibration
10/15/2008CN201134264Y USB storage device displaying capacity
10/15/2008CN101286367A FPGA built-in dual port memory test method
10/15/2008CN101286366A Semiconductor integrated circuit and memory checking method
10/15/2008CN101286358A System and device with error detection/correction process and method outputting data
10/15/2008CN101286356A Non-volatile memorizer process fluctuation control method
10/14/2008US7437658 Disk array device, parity data generating circuit for RAID and Galois field multiplying circuit
10/14/2008US7437652 Correcting multiple block data loss in a storage array using a combination of a single diagonal parity group and multiple row parity groups
10/14/2008US7437651 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem
10/14/2008US7437647 Mode entry circuit and method
10/14/2008US7437645 Test circuit for semiconductor device
10/14/2008US7437637 Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing
10/14/2008US7437632 Circuits and methods for repairing defects in memory devices
10/14/2008US7437631 Soft errors handling in EEPROM devices
10/14/2008US7437630 Testing a multibank memory module
10/14/2008US7437629 Method for checking the refresh function of an information memory
10/14/2008US7437627 Method and test device for determining a repair solution for a memory module
10/14/2008US7437626 Efficient method of test and soft repair of SRAM with redundancy
10/14/2008US7437625 Memory with element redundancy
10/14/2008US7437602 Memory card apparatus configured to provide notification of memory capacity
10/14/2008US7437531 Testing memories
10/14/2008US7437258 Use of I2C programmable clock generator to enable frequency variation under BMC control
10/14/2008US7436718 Semiconductor memory device including fuse detection circuit to determine successful fuse-cutting rate for optical fuse-cutting conditions
10/14/2008US7436712 Nonvolatile memory device including circuit formed of thin film transistors
10/14/2008US7435927 Semiconductor link processing using multiple laterally spaced laser beam spots with on-axis offset
10/09/2008WO2008121426A2 Testing for sram memory data retention
10/09/2008WO2008120389A1 Memory test circuit, semiconductor integrated circuit and memory test method
10/09/2008US20080247247 Flash memory device and method for driving the same
10/09/2008DE102008016205A1 Verfahren und Schaltung zur Belastung von Zwischenverbindungen auf hoher Ebene in Halbleiterbauelementen Method and circuit for load of high-level interconnects in semiconductor devices
10/09/2008DE102007016622A1 Halbleiter-Bauelement-Test-Verfahren und -Test-System mit reduzierter Anzahl an Test-Kanälen A semiconductor device testing method and test system with a reduced number of test channels,
10/09/2008DE102007013062A1 Vorrichtung und Verfahren zur elektrischen Kontaktierung zum Testen von Halbleiter-Bauelementen Apparatus and method for making electrical contact for testing of semiconductor devices
10/08/2008EP1978527A1 Tester
10/08/2008EP1978446A1 Compressing test responses using a compactor
10/08/2008EP1543526B1 Method of recovering overerased bits in a memory device
10/08/2008CN101281788A Flash memory system as well as control method thereof
10/08/2008CN100424781C Multi-mode synchronous memory device and methods of operating and testing same
10/08/2008CN100424518C Semiconductor test instrument
10/07/2008US7434151 Read control systems and methods
10/07/2008US7434141 Network-based memory error decoding system and method
10/07/2008US7434140 Apparatus for accessing and transferring optical data
10/07/2008US7434136 Method of and apparatus for reading recording medium, harddisk controller
10/07/2008US7434130 Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection
10/07/2008US7434125 Integrated circuit, test system and method for reading out an error datum from the integrated circuit
10/07/2008US7434122 Flash memory device for performing bad block management and method of performing bad block management of flash memory device
10/07/2008US7434121 Integrated memory device and method for its testing and manufacture
10/07/2008US7434120 Test mode control circuit
10/07/2008US7434119 Method and apparatus for memory self testing
10/07/2008US7434095 Data reconstruction method and system wherein timing of data of data reconstruction is controlled in accordance with conditions when a failure occurs
10/07/2008US7433995 Method for updating memory
10/07/2008US7433976 Data copy method and application processor for the same
10/07/2008US7433252 Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device
10/07/2008US7433251 Semiconductor memory device storing redundant replacement information with small occupation area
10/02/2008WO2008118832A1 Self-test output for high-density bist
10/02/2008WO2008118717A1 Sharing routing of a test signal with an alternative power supply to combinatorial logic for low power design
10/02/2008WO2008117921A1 Read level control apparatuses and methods
10/02/2008WO2008117381A1 Tester and electronic device
10/02/2008WO2008117380A1 Semiconductor integrated circuit device and its test method
10/02/2008US20080244340 Test apparatus and selection apparatus
10/02/2008US20080244338 Soft bit data transmission for error correction control in non-volatile memory
10/02/2008US20080239844 Implementing calibration of dqs sampling during synchronous dram reads
10/02/2008US20080239609 Method and apparatus providing final test and trimming for a power supply controller
10/02/2008DE102008015703A1 Integrierter Schaltungschip und Verfahren zum Testen eines integrierten Schaltungschips The integrated circuit chip and method for testing an integrated circuit chip
10/02/2008DE102007017642A1 Prüfschaltungsanordnung Test circuit
10/02/2008DE102007015284A1 Test card for testing e.g. programmable logic array, has contact test piece comprising drill bit that is equipped with cutting edge, where device allows drill bit to penetrate into semiconductor component
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