Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/2008
11/13/2008DE102008021640A1 Schaltung und Verfahren zum Finden von Wortleitung-Bitleitung-Kurzschlüssen in einem DRAM Circuit and method for finding word line-bit line short circuits in a DRAM
11/13/2008DE102008021414A1 Flexibles Redundanzersetzungsschema für ein Halbleiterbauteil Flexible redundancy replacement scheme for a semiconductor device
11/12/2008EP1990805A1 Ram macro and timing generating circuit for same
11/12/2008EP1989713A2 At-speed multi-port memory array test method and apparatus
11/12/2008EP1989562A1 Dual-path, multimode sequential storage element
11/12/2008CN101303899A Method and apparatus for repairing memory
11/12/2008CN101303898A Circuit and method for self repairing multiport memory
11/12/2008CN101303897A Memory structure, repair system and method for testing the same
11/12/2008CN100433446C Cell evaluation device
11/11/2008US7451387 Autonomous method and apparatus for mitigating soft-errors in integrated circuit memory storage devices at run-time
11/11/2008US7451380 Method for implementing enhanced vertical ECC storage in a dynamic random access memory
11/11/2008US7451370 Input/output buffer test circuitry and leads additional to boundary scan
11/11/2008US7451368 Semiconductor device and method for testing semiconductor device
11/11/2008US7451367 Accessing sequential data in microcontrollers
11/11/2008US7451366 Nonvolatile memory devices with test data buffers and methods for testing same
11/11/2008US7451364 Method and apparatus for managing disc defects using updateable DMA, and disc thereof
11/11/2008US7451363 Semiconductor integrated circuit including memory macro
11/11/2008US7451360 Method for monitoring an internal control signal of a memory device and apparatus therefor
11/11/2008US7451146 Almost non-blocking linked stack implementation
11/11/2008US7450459 Multi-port memory device
11/11/2008US7450449 Semiconductor memory device and its test method
11/06/2008WO2008133680A1 Embedded memory repair on the basis of fuse burn state machine and a fus download state machine
11/06/2008WO2008133678A1 Memory device with error correction capability and efficient partial word write operation
11/06/2008WO2008133087A1 Semiconductor storage device and its operation method
11/06/2008WO2008133040A1 Semiconductor device
11/06/2008WO2008089157A3 Column leakage compensation in a sensing circuit
11/06/2008WO2007112201A9 Non-volatile memory and method with redundancy data buffered in data latches for defective locations
11/06/2008US20080276152 System and Method for Error Detection in a Data Storage System
11/06/2008US20080273408 System for bitcell and column testing in sram
11/06/2008US20080273406 Enhanced sram redundancy circuit for reducing wiring and required number of redundant elements
11/06/2008DE10319273B4 Verfahren und Vorrichtung zum Bewerten und Nachprogrammieren von einmal programmierbaren Zellen Method and apparatus for evaluating and reprogramming of one-time programmable cells
11/06/2008DE102006061012B4 Interne Spannungsüberwachung beim Testen von Wafern Internal voltage monitoring during testing of wafers
11/05/2008EP1988468A1 Ram diagnosis apparatus and ram diagnosis method
11/05/2008CN100431056C Non-volatile memory test structure and method
11/05/2008CN100431055C Enhanced special programming mode
11/05/2008CN100431048C Semiconductor memory device for producing inner data readout time sequence in inner part
11/05/2008CN100431045C Non-volatile semiconductor memory
11/05/2008CN100431035C Method for managing shortage position in data storage medium and recording medium
11/05/2008CN100430900C Error corrector
11/04/2008US7447976 Data transfer apparatus
11/04/2008US7447974 Memory controller method and system compensating for memory cell data losses
11/04/2008US7447973 Memory controller method and system compensating for memory cell data losses
11/04/2008US7447960 Method of efficiently loading scan and non-scan memory elements
11/04/2008US7447959 Semiconductor integrated circuit and a method of testing the same
11/04/2008US7447957 Dynamic soft-error-rate discrimination via in-situ self-sensing coupled with parity-space detection
11/04/2008US7447956 Method and apparatus for testing data steering logic for data storage having independently addressable subunits
11/04/2008US7447955 Test apparatus and test method
11/04/2008US7447954 Method of testing a memory module and hub of the memory module
11/04/2008US7447953 Lane testing with variable mapping
11/04/2008US7447952 Method of and apparatus for managing disc defects using temporary defect management information (TDFL) and temporary defect management information (TDDS), and disc having the TDFL and TDDS
11/04/2008US7447951 Information storage medium, method of managing replacement information, recording/reproducing apparatus, and host apparatus
11/04/2008US7447950 Memory device and memory error correction method
11/04/2008US7447936 Nonvolatile memory system
11/04/2008US7447087 Semiconductor memory device having memory block configuration
11/04/2008US7447072 Storage device employing a flash memory
11/04/2008US7447069 Flash EEprom system
11/04/2008US7447060 MRAM Memory conditioning
10/2008
10/30/2008WO2008131347A1 Jtag controlled self-repair after packaging
10/30/2008WO2008131137A2 Programmable floating gate reference
10/30/2008WO2008093257A3 Method of protecting against attacks and circuit therefor
10/30/2008WO2007112163A3 Error correction device and methods thereof
10/30/2008WO2007038233A3 Strobe technique for test of digital signal timing
10/30/2008US20080270870 Memory Controller and Method for Implementing Minimized Latency and Maximized Reliability When Data Traverses Multiple Buses
10/30/2008US20080270869 Data reproducing apparatus
10/30/2008US20080270855 Method For Detecting Memory Error
10/30/2008US20080270854 System and method for running test and redundancy analysis in parallel
10/30/2008US20080266991 Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache
10/30/2008US20080266985 Methods and apparatus for testing integrated circuits
10/30/2008DE112006003381T5 Reparatur-BITS für Niederspannungs-Cache Repair bits for low-voltage cache
10/30/2008DE102008020190A1 Speicherredundanzverfahren und -vorrichtung Memory redundancy method and apparatus
10/29/2008EP1986233A2 On-chip reconfigurable memory
10/29/2008EP1579483A4 System and method for expanding a pulse width
10/29/2008CN101295537A Reading operation control method of memory body
10/28/2008US7444581 Error handling of storage device data in real time systems
10/28/2008US7444580 System and method for interleaving data in a communication device
10/28/2008US7444579 Non-systematic coded error correction
10/28/2008US7444566 Memory device fail summary data reduction for improved redundancy analysis
10/28/2008US7444564 Automatic bit fail mapping for embedded memories with clock multipliers
10/28/2008US7444563 Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
10/28/2008US7444562 Trie-type memory device with a compression mechanism
10/28/2008US7444560 Test clocking scheme
10/28/2008US7444559 Generation of memory test patterns for DLL calibration
10/28/2008US7444557 Memory with fault tolerant reference circuitry
10/28/2008US7444556 System and method of interleaving transmitted data
10/28/2008US7444497 Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support
10/28/2008US7444490 Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress
10/28/2008US7444467 Storage system having a semiconductor memory device which stores data and parity data permanently
10/28/2008US7443745 Byte writeable memory with bit-column voltage selection and column redundancy
10/28/2008US7442959 Semiconductor device having identification number, manufacturing method thereof and electronic device
10/23/2008WO2008127616A1 Method and apparatus for testing page decoder
10/23/2008WO2008126747A1 Test apparatus, test method, and electronic device
10/23/2008WO2008126548A1 Method for evaluating sram memory cell and medium recording evaluation program of sram memory cell computer readably
10/23/2008WO2008126165A1 Test device
10/23/2008US20080263429 Method and Device for Correcting Code Data Error
10/23/2008US20080263417 Efficient Memory Product for Test and Soft Repair of SRAM with Redundancy
10/23/2008US20080263416 Method and apparatus to adjust voltage for storage location reliability
10/23/2008US20080263415 Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Fabricating an Integrated Circuit, Computer Program Product, and Computing System
10/23/2008US20080263414 Semiconductor device and data processing system
10/23/2008US20080259705 Hardware and software programmable fuses for memory repair
10/23/2008US20080259703 Self-timed synchronous memory
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