Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
12/2009
12/17/2009US20090313513 Apparatus and method for testing semiconductor memory device
12/17/2009US20090313511 Semiconductor device testing
12/17/2009US20090310430 Methods for characterizing device variation in electronic memory circuits
12/16/2009CN101606131A Memory system and method for storing and correcting data
12/16/2009CN100570754C Error correcting information processing method in BCH error correcting technology and processing equipment thereof
12/16/2009CN100570753C Apparatus and method for storing array redundancy data on integrated circuit device
12/16/2009CN100570752C Method for testing memory
12/16/2009CN100570751C Memory array and method for testing the same
12/16/2009CN100570750C Semiconductor memory and preburning test method of semiconductor memory
12/16/2009CN100570748C On-chip EE-PROM programming waveform generation
12/16/2009CN100570745C Storage integrate circuit
12/16/2009CN100570743C Single wafer magnetic resistance type memory
12/15/2009US7634713 Error detection and location circuitry for configuration random-access memory
12/15/2009US7634709 Familial correction with non-familial double bit error detection
12/15/2009US7634707 Error detection/correction method
12/15/2009US7634699 System and method for testing a data storage device without revealing memory content
12/15/2009US7634698 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
12/15/2009US7634697 Semiconductor memory device, memory system having semiconductor memory device, and method for testing memory system
12/15/2009US7634696 System and method for testing memory
12/15/2009US7634695 Test apparatus and selection apparatus
12/15/2009US7633826 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used
12/15/2009US7633819 Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator
12/15/2009CA2646220C Test circuit for an unprogrammed otp memory array
12/10/2009WO2009149160A1 Method and apparatus for securing digital information on an integrated circuit during test operating modes
12/10/2009WO2009147786A1 Test apparatus and testing method
12/10/2009US20090307563 Replacing bad hard drive sectors using mram
12/10/2009US20090307544 Memory test device and memory test method
12/10/2009US20090307543 Transport subsystem for an mbist chain architecture
12/10/2009US20090307538 Managing Paging I/O Errors During Hypervisor Page Fault Processing
12/10/2009US20090303818 Test circuit device for semiconductor memory apparatus
12/10/2009US20090303817 Leakage testing method for dynamic random access memory having a recess gate
12/10/2009US20090303816 Semiconductor memory apparatus and method of controlling redundancy thereof
12/10/2009US20090303815 Apparatus for redundancy reconfiguration of faculty memories
12/10/2009US20090303814 Integrated circuit that stores defective memory cell addresses
12/10/2009DE10220328B4 Schaltung zur Taktsignalerzeugung, zugehörige integrierte Schaltkreisbauelemente und Auffrischtaktsteuerverfahren Circuit for clock signal generation, associated integrated circuit devices and Auffrischtaktsteuerverfahren
12/09/2009CN101601098A Monitor burn-in test device and monitor burn-in test method
12/09/2009CN101601094A Reading memory cells using multiple thresholds
12/09/2009CN101599306A Field mounting-type test apparatus and method
12/09/2009CN101599305A Storage system with data-restoring function and data-restoring method thereof
12/09/2009CN100568397C Production and test approach for internal memory performance
12/09/2009CN100568396C Method for current sense amplifier calibration in MRAM devices
12/09/2009CN100568395C Non-volatile memory and accelerated test method for address decoder by adding modified dummy memory cells
12/09/2009CN100568394C Multi-time programmable semiconductor memory device and multi-time programming method therefor
12/08/2009US7631245 NAND flash memory controller exporting a NAND interface
12/08/2009US7631244 Soft error correction method, memory control apparatus and memory system
12/08/2009US7631236 Hybrid built-in self test (BIST) architecture for embedded memory arrays and an associated method
12/08/2009US7631234 Test apparatus and test method
12/08/2009US7631233 Data inversion register technique for integrated circuit memory testing
12/08/2009US7631232 Parallel burning system and method
12/08/2009US7631231 Method and apparatus for testing the connectivity of a flash memory chip
12/08/2009US7630259 Programmable logic device with built in self test
12/08/2009US7630258 Decoder based set associative repair cache systems and methods
12/08/2009US7630178 Semiconductor integrated circuit
12/08/2009US7629234 Semiconductor structure processing using multiple laterally spaced laser beam spots with joint velocity profiling
12/03/2009US20090300466 Error correction method and error correction circuit
12/03/2009US20090300445 Method and system for alternating between programs for execution by cells of an integrated circuit
12/03/2009US20090300444 Method and apparatus for testing high capacity/high bandwidth memory devices
12/03/2009US20090300442 Field mounting-type test apparatus and method for testing memory component or module in actual PC environment
12/03/2009US20090300441 Address controlling in the mbist chain architecture
12/03/2009US20090300440 Data controlling in the mbist chain architecture
12/03/2009US20090300439 Method and Apparatus for Testing Write-Only Registers
12/03/2009US20090300413 Disabling portions of memory with defects
12/03/2009US20090296505 Memory test method and memory test device
12/03/2009US20090296504 Semiconductor memory device and method of testing semiconductor memory device
12/03/2009US20090296496 Method and circuit for testing a multi-chip package
12/03/2009DE112008000429T5 Prüfvorrichtung und Prüfverfahren Tester and test methods
12/03/2009DE102008022428A1 Integrated memory i.e. Dynamic RAM, module, for selective writing and reading of data bits, has amplifier-selection circuit switched between normal and test modes to switch all amplifiers in normal mode and preselected subsets in test mode
12/02/2009CN101594133A Semiconductor integrated circuit, control method, and information processing apparatus
12/02/2009CN101593563A Memory chip and method for operating the same
12/02/2009CN101593562A Method and circuit for testing a multi-chip package
12/02/2009CN100565703C Device and method for regenerating information stored in memory medium
12/01/2009US7627796 Testing method for permanent electrical removal of an integrated circuit output
12/01/2009US7627795 Pipelined data processor with deterministic signature generation
12/01/2009US7627793 Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems
12/01/2009US7627792 Memory built-in self repair (MBISR) circuits/devices and method for repairing a memory comprising a memory built-in self repair (MBISR) structure
12/01/2009US7627791 Method and apparatus for recording a data stream on a storage medium
12/01/2009US7627773 Logic circuit and semiconductor integrated circuit
12/01/2009US7627715 Concentrated parity technique for handling double failures and enabling storage of more than one parity block per stripe on a storage device of a storage array
12/01/2009US7626908 Target track seeking for data recording and reproducing system
12/01/2009US7626876 Semiconductor memory device and its test method
12/01/2009US7626875 Multi-wordline test control circuit and controlling method thereof
12/01/2009US7626852 Adaptive voltage control for SRAM
11/2009
11/26/2009WO2009141849A1 Pattern generator
11/26/2009WO2009141848A1 Pattern generator and memory testing device using the same
11/26/2009US20090292974 Method and apparatus for iterative error-erasure decoding
11/26/2009US20090292971 Data recovery techniques
11/26/2009US20090292970 Using error information from nearby locations to recover uncorrectable data in non-volatile memory
11/26/2009US20090292944 Adaptive Deterministic Grouping of Blocks into Multi-Block Units
11/26/2009US20090290442 Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies
11/26/2009US20090290441 Memory block testing
11/26/2009US20090290440 Row Addressing
11/26/2009US20090290435 Nonvolatile memory device and method of testing the same
11/26/2009DE10352398B4 Soft-Error-Verbesserung für Latch-Schaltung in einem DRAM Soft error improvement for latch circuit in a DRAM
11/25/2009CN101587754A Memorizer test device based on scan chain and use method thereof
11/25/2009CN101587744A Multi-level data redundancy method of large scale FLASH memory array
11/24/2009USRE41013 Method of and apparatus for providing look ahead column redundancy access within a memory
11/24/2009US7624329 Programming a memory device having error correction logic
11/24/2009US7624319 Performance monitoring system
11/24/2009US7624318 Method and apparatus for automatically identifying multiple combinations of operational and non-operational components on integrated circuit chips with a single part number
11/24/2009US7624317 Parallel bit test circuit and method for semiconductor memory device
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