Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
09/2010
09/15/2010CN101833998A Memory bank testing device
09/15/2010CN101354906B Flash memory controller for solid hard disk
09/15/2010CN101042936B Programmable non-volatile memory device and method for testing and operating same
09/14/2010US7797612 Storage accelerator
09/14/2010US7797611 Creating an error correction coding scheme and reducing data loss
09/14/2010US7797610 Method and apparatus for virtual quad-port random access memory
09/14/2010US7797597 Error detection, documentation, and correction in a flash memory device
09/14/2010US7797596 Method for monitoring and adjusting circuit performance
09/14/2010US7797595 Serially decoded digital device testing
09/14/2010US7797594 Built-in self-test of 3-dimensional semiconductor memory arrays
09/14/2010US7797593 Method and apparatus for memory AC timing measurement
09/14/2010US7797591 Semiconductor integrated circuit, design support software system, and automatic test pattern generation system
09/14/2010US7797134 System and method for testing a memory with an expansion card using DMA
09/14/2010US7796451 Integrated circuits and methods to compensate for defective memory in multiple layers of memory
09/10/2010WO2010102235A1 Fault diagnosis for non-volatile memories
09/09/2010US20100229056 System and Method for Increasing the Extent of Built-In Self-Testing of Memory and Circuitry
09/09/2010US20100229055 Fault Diagnosis For Non-Volatile Memories
09/09/2010US20100226190 Sram and testing method of sram
09/09/2010DE102009010886A1 Erkennung der Verzögerungszeit in einem eingebauten Speicherselbsttest unter Anwendung eines Ping-Signals Detecting the delay time in a built-in memory self-test using a Ping signal
09/09/2010DE102009001352A1 Device for e.g. detecting hardware error during addressing memory cell matrix in safety-critical user-specific integrated circuits, has test memory cell attached to memory cell, where code word is formed from address and parity bits
09/08/2010EP2225633A2 Data parallel production and consumption
09/08/2010CN201576463U Device for producing and displaying bitmap information during embedded flash memory testing process
09/08/2010CN1855297B Nonvolatile ferroelectric memory device including failed cell correcting circuit
09/08/2010CN101826368A Data scanning method and scanning device
09/08/2010CN101826367A Method and device for monitoring reliability of semiconductor storage device
09/08/2010CN101171644B Method and apparatus for transmitting data
09/08/2010CN101004953B Disabling faulty flash memory dies
09/07/2010USRE41659 Methods and circuitry for built-in self-testing of content addressable memories
09/07/2010US7793192 Semiconductor memory device
09/07/2010US7793186 System and method for increasing the extent of built-in self-testing of memory and circuitry
09/07/2010US7793175 Automated scan testing of DDR SDRAM
09/07/2010US7793174 Semiconductor apparatus and test method therefor
09/07/2010US7793173 Efficient memory product for test and soft repair of SRAM with redundancy
09/07/2010US7793172 Controlled reliability in an integrated circuit
09/07/2010US7793170 Method and apparatus for combining de-interleaving with FFT and demapping
09/07/2010US7793035 Memory system and controller
09/07/2010US7791969 Method and apparatus for screening bit line of a static random access memory (SRAM) for excessive leakage current
09/07/2010US7791968 Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator
09/07/2010US7791967 Semiconductor memory device and method of testing the same
09/07/2010US7791966 Apparatus, memory device and method of improving redundancy
09/02/2010US20100223514 Semiconductor memory device
09/02/2010US20100223513 Latency detection in a memory built-in self-test by using a ping signal
09/02/2010US20100223512 System, apparatus, and method for memory built in self testing using microcode sequencers
09/02/2010US20100223511 At-speed bitmapping in a memory built-in self-test by locking an n-th failure
09/02/2010US20100223510 Nonvolatile memory device, nonvolatile memory system, and defect management method for nonvolatile memory device
09/02/2010US20100220538 Integrated circuit memory power supply
09/02/2010US20100220534 Memory Device with Reduced Buffer Current During Power-Down Mode
09/02/2010US20100220532 Readout Circuit for Rewritable Memories and Readout Method for Same
09/02/2010US20100220519 Sensing Characteristic Evaluating Apparatus for Semiconductor Device and Method Thereof
09/02/2010US20100220515 Semiconductor memory device and test method therefor
09/02/2010DE102010007001A1 System und Verfahren zum Erstellen eines Multi-Write-Fehlerkorrekturcodes System and method for creating a multi-write error-correcting codes
09/02/2010DE102010001421A1 Speichertestsystem, Speichersystem, Verfahren zum Testen einer Mehrzahl von integrierten Schaltkreisen und Verfahren zum Herstellen eines Speicherelements A memory test system, storage system, method for testing a plurality of integrated circuits and methods for manufacturing a memory element
09/02/2010DE102009010881A1 Beschleunigte Bitkartenerzeugung bei der eingebauten Speicherselbstprüfung durch Verriegeln eines N-ten Fehlers Accelerated Bitkartenerzeugung in the built-in memory self-test by locking an Nth error
09/02/2010DE102006007439B4 Halbleitereinzelchip, System und Verfahren zum Testen von Halbleitern unter Verwendung von Einzelchips mit integrierten Schaltungen Semiconductor die, system and method for testing semiconductors using single chips with integrated circuits
09/01/2010EP2224451A1 Disabling faulty flash memory dies
09/01/2010CN1819062B Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of sram with redundancy
09/01/2010CN101819821A Dynamic loss balancing method for solid state disk
09/01/2010CN101819810A Semiconductor memory device and system
09/01/2010CN101197195B Data coding and decoding method and device in NOT-AND flash memory device
08/2010
08/31/2010US7788569 Autonomic parity exchange
08/31/2010US7788557 Baseboard testing interface and testing method thereof
08/31/2010US7788555 Using fractional sectors for mapping defects in disk drives
08/31/2010US7788554 Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation
08/31/2010US7788553 Mass production testing of USB flash cards with various flash memory cells
08/31/2010US7788550 Redundant bit patterns for column defects coding
08/31/2010US7788549 Apparatus and method for defect replacement
08/31/2010US7788548 Method for performing a defective-area management in an optical media
08/31/2010US7788506 Method and device for protecting a memory against attacks by error injection
08/31/2010US7787318 Semiconductor memory device having read operation testing function
08/31/2010US7787317 Memory circuit and tracking circuit thereof
08/31/2010US7787300 Memory devices with page buffer having dual registers and method of using the same
08/31/2010US7787296 Nonvolatile semiconductor memory device having protection function for each memory block
08/26/2010WO2010078540A3 Spare block management in non-volatile memories
08/26/2010US20100218057 Control method for semiconductor integrated circuit and semiconductor integrated circuit
08/26/2010US20100218056 Method and system for performing a double pass nth fail bitmap of a device memory
08/26/2010US20100218054 Secure Scan Design
08/26/2010US20100214832 Phase-change random access memory
08/25/2010EP2221830A1 Memory device and wear leveling method thereof
08/25/2010EP2221827A1 Maintenance operations for multi-level data storage cells
08/25/2010CN201562462U Device for testing multiport memory device to detect fault of multiport memory
08/25/2010CN1983451B Semiconductor memory device
08/25/2010CN101814922A Multi-bit error correcting method and device based on BCH (Broadcast Channel) code and memory system
08/25/2010CN101814324A Method for reducing leakage current of memory and memory access method
08/25/2010CN101814323A Verification circuit and method of phase change memory array
08/25/2010CN101814317A Phase change storage
08/24/2010US7783957 Apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory
08/24/2010US7783956 Data recorder
08/24/2010US7783955 Method for implementing error-correction codes in flash memory
08/24/2010US7783944 Semiconductor memory device and method thereof
08/24/2010US7783943 Method and apparatus for testing a random access memory device
08/24/2010US7783942 Integrated circuit device with built-in self test (BIST) circuit
08/24/2010US7783941 Memory devices with error detection using read/write comparisons
08/24/2010US7783940 Apparatus for redundancy reconfiguration of faculty memories
08/24/2010US7783939 Cache memory, processor, and production methods for cache memory and processor
08/24/2010US7783936 Memory arbitration technique for turbo decoding
08/24/2010US7783935 Bit error rate reduction buffer
08/24/2010US7782689 Semiconductor integrated circuit and memory checking method
08/24/2010US7782687 Semiconductor device
08/24/2010US7782672 Semiconductor memory device having memory block configuration
08/24/2010US7782083 Trimming circuits and methods
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