Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
03/1996
03/26/1996US5502672 Data output buffer control circuit
03/26/1996US5502645 Behavioral synthesis for reconfigurable datapath structures
03/26/1996US5502395 Method for programming antifuses for reliable programmed links
03/21/1996WO1996008840A1 A flash eprom transistor array and method for manufacturing the same
03/21/1996WO1996008822A2 Sense amplifier for non-volatile semiconductor memory
03/21/1996DE19506542C1 Power-on self test for personal computer work-station memory
03/20/1996EP0702373A1 Redundant address memory and test method therefor
03/20/1996EP0702238A1 On-chip oscillator and test method therefor
03/20/1996EP0701733A1 A burst mode memory accessing system
03/20/1996CN1118924A Memory assembly, odd-even check bit emulator and odd-even check bit emulating method
03/19/1996US5500826 Solid state peripheral storage device
03/19/1996US5500824 Adjustable cell plate generator
03/19/1996US5500823 Memory defect detection arrangement
03/19/1996US5500822 Address decoder for repair of memory device
03/19/1996US5500821 Semiconductor memory device
03/14/1996WO1996007969A1 On board error correction apparatus
03/14/1996DE19529691A1 Semiconductor memory with test mode
03/14/1996DE19520630A1 Wafer burn-in test circuit for sensing defective cell of semiconductor memory device
03/13/1996EP0701259A2 Auto-program circuit for a non-volatile memory device
03/13/1996EP0701212A2 Data processor with address translation mechanism
03/13/1996EP0701210A2 Data processor having data bus and instruction fetch bus provided separately from each other
03/13/1996EP0505652B1 Memory system with adaptable redundancy
03/13/1996CN1118519A Semiconductor memory device
03/12/1996US5499385 Method for accessing and transmitting data to/from a memory in packets
03/12/1996US5499250 System having multiple subsystems and test signal source resident upon common substrate
03/12/1996US5499249 Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs)
03/12/1996US5499248 Test vector generator comprising a decompression control unit and a conditional vector processing unit and method for generating a test vector
03/12/1996US5499211 Bit-line precharge current limiter for CMOS dynamic memories
03/12/1996US5498990 Reduced CMOS-swing clamping circuit for bus lines
03/12/1996US5498886 Circuit module redundancy architecture
03/10/1996CA2131735A1 Board errors correction apparatus
03/06/1996EP0699999A2 Memory architecture for automatic test equipment using vector module table
03/05/1996US5497459 System for testing instruction queue circuit and central processing unit having the system
03/05/1996US5497458 Cache testability circuit for embedded diagnostics
03/05/1996US5497378 System and method for testing a circuit network having elements testable by different boundary scan standards
03/05/1996US5497376 Method and device for detecting and correcting errors in memory modules
03/05/1996US5497353 Semiconductor memory device
03/05/1996US5497350 Integrated semiconductor memory device capable of switching from a memory mode to an internal test mode
03/05/1996US5497348 Burn-in detection circuit
03/05/1996US5497347 BICMOS cache TAG comparator having redundancy and separate read an compare paths
03/05/1996US5497117 Input sense circuit having selectable thresholds
03/05/1996US5497079 Semiconductor testing apparatus, semiconductor testing circuit chip, and probe card
02/1996
02/29/1996DE19530660A1 Microcomputer system with direct or indirect communication with EEPROM
02/28/1996EP0698891A1 Testing a non-volatile memory
02/28/1996EP0698890A1 Testing an integrated circuit device
02/28/1996EP0698889A1 Memory device
02/28/1996EP0698848A1 Method and apparatus for testing an integrated circuit
02/28/1996EP0698273A1 Memory iddq-testable through cumulative word line activation
02/27/1996US5495572 Data reconstruction method and system wherein timing of data reconstruction is controlled in accordance with conditions when a failure occurs
02/27/1996US5495491 System using a memory controller controlling an error correction means to detect and correct memory errors when and over a time interval indicated by registers in the memory controller
02/27/1996US5495448 Memory testing through cumulative word line activation
02/27/1996US5495447 Method and apparatus using mapped redundancy to perform multiple large block memory array repair
02/27/1996US5495446 Pre-charged exclusionary wired-connected programmed redundant select
02/27/1996US5495445 Redundancy scheme for memory circuits
02/22/1996WO1996005191A1 Natriuretic cyclic compounds
02/22/1996DE4429633A1 Memories monitoring method for EEPROM and battery buffered memory
02/21/1996EP0697702A2 Semiconductor memory device and high-voltage switching circuit
02/21/1996EP0697660A1 HMC: a hybrid mirrored and chained data replication method to support high availability for disk arrays
02/21/1996EP0697659A1 Redundancy circuit for an integrated circuit semiconductor memory
02/21/1996CN1117193A Method and circuit for preparing defect in semiconductor memory device
02/21/1996CN1117167A Apparatus for generating address data
02/21/1996CN1031084C Computer controlled optimized pairing of disk units
02/21/1996CN1031083C Memory card resident diagnostic testing
02/20/1996US5493676 Severe environment data recording system
02/20/1996US5493532 Integrated circuit memory with disabled edge transition pulse generation during special test mode
02/20/1996US5493531 Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device
02/14/1996CN1116755A Active matrix panel and method for fabricating the same
02/14/1996CN1116710A Wafer burn-in test circuit of a semiconductor memory device
02/13/1996US5491665 IDDQ -testable RAM
02/13/1996US5491664 Flexibilitiy for column redundancy in a divided array architecture
02/13/1996US5491662 Microcontroller memory cell current reading method
02/13/1996US5491660 On-chip operation control for memories
02/13/1996US5491655 Semiconductor memory device having non-selecting level generation circuitry for providing a low potential during reading mode and high level potential during another operation mode
02/13/1996US5491444 Fuse circuit with feedback disconnect
02/13/1996US5491359 Microcomputer with high density ram in separate isolation well on single chip
02/07/1996EP0696031A1 Programmable integrated memory with emulation means
02/06/1996US5490264 Generally-diagonal mapping of address space for row/column organizer memories
02/06/1996US5490115 Method and apparatus for writing to memory cells in a minimum number of cycles during a memory test operation
02/06/1996US5490107 Nonvolatile semiconductor memory
02/01/1996WO1996002917A1 Testing of memory content
02/01/1996WO1996002916A1 Memory with stress circuitry for detecting defects
02/01/1996DE4427108A1 Kraftfahrzeug-Steuergerät Motor vehicle control device
02/01/1996CA2194289A1 Testing of memory content
01/1996
01/31/1996EP0694840A2 Motor vehicle controller using electrically erasable and programmable memory
01/31/1996EP0427260B1 Non-volatile memory devices
01/31/1996CN1030868C Adapter for constructing redundant disk storage system
01/30/1996US5488731 Multiprocessor system
01/30/1996US5488701 In log sparing for log structured arrays
01/30/1996US5488583 Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits
01/30/1996US5488578 Semiconductor memory device including bit check function and testing method using the same
01/23/1996US5487045 Sense amplifier having variable sensing load for non-volatile memory
01/23/1996US5487042 Semiconductor integrated circuit device equipped with answer system for teaching optional functions to diagnostic system
01/23/1996US5487041 For increasing the operating speed of a cache memory
01/23/1996US5487040 Semiconductor memory device and defective memory cell repair circuit
01/23/1996US5487039 Semiconductor memory device
01/23/1996US5487036 Nonvolatile semiconductor memory
01/23/1996US5486766 Method for testing switch matrices
01/17/1996CN1115104A Row redundancy circuit and method for a semiconductor memory device with a double row decoder
01/16/1996US5485571 In a computer system
01/16/1996US5485474 Scheme for information dispersal and reconstruction