Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
09/1996
09/11/1996EP0438273B1 Semiconductor memory devices having column redundancy
09/10/1996US5555522 Semiconductor memory having redundant cells
09/10/1996US5555371 Data backup copying with delayed directory updating and reduced numbers of DASD accesses at a back up site using a log structured array data storage
09/10/1996US5555249 Non-destructive memory testing in computers
09/10/1996US5555212 Method and apparatus for redundancy word line replacement in a semiconductor memory device
09/10/1996US5554553 Highly compact EPROM and flash EEPROM devices
09/04/1996EP0730231A2 Semiconductor memory with cells grouped into individually addressable units, and its method of operation
09/04/1996EP0729633A1 Sense amplifier for non-volatile semiconductor memory
09/04/1996EP0163580B1 Semiconductor integrated circuit with redundant circuit replacement
09/03/1996US5553238 Powerfail durable NVRAM testing
09/03/1996US5553233 Management apparatus for volume-medium correspondence information for use in dual file system
09/03/1996US5553232 Automated safestore stack generation and move in a fault tolerant central processor
09/03/1996US5553231 Fault tolerant memory system
09/03/1996US5553082 Built-in self-test for logic circuitry at memory array output
09/03/1996US5553026 Non-volatile semiconductor memory device
09/03/1996US5553025 Semiconductor memory device executing a memory test in a plurality of test modes
09/03/1996US5553023 In a computer system
09/03/1996US5552743 Thin film transistor redundancy structure
08/1996
08/29/1996WO1996026523A1 An iterative method of recording analog signals
08/29/1996DE19606637A1 Integrated circuit test device for e.g. semiconductor memory
08/29/1996DE19506957A1 Actualization and loading method for application programs in microprocessor memory
08/28/1996EP0729100A1 Cache testing using a modified snoop cycle command
08/28/1996EP0729099A1 Mirror storage controller
08/28/1996EP0729034A2 Test circuit and process for functional testing electronic circuits
08/28/1996EP0728367A1 A flash eprom transistor array and method for manufacturing the same
08/27/1996US5551004 Structure which renders faulty data of a cache memory uncacheable in order that a partially functional cache memory may be utilized
08/27/1996US5550986 Data storage device matrix architecture
08/27/1996US5550974 Testable memory array which is immune to multiple wordline assertions during scan testing
08/27/1996US5550973 In a computer network
08/27/1996US5550846 Circuit for generating an output sequence of values
08/27/1996US5550842 EEPROM verification circuit with PMOS transistors
08/27/1996US5550838 Method for testing characteristics of a semiconductor memory device in a series of steps
08/27/1996US5550776 Semiconductor memory device capable of driving word lines at high speed
08/27/1996US5550394 Semiconductor memory device and defective memory cell correction circuit
08/22/1996WO1996025744A1 On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same
08/22/1996DE19604764A1 Semiconductor memory structure for DRAM, VSRAM and PSRAM
08/22/1996CA2218178A1 Multi-purpose transaction card system
08/21/1996EP0727785A1 Enhanced self-test of memories
08/21/1996EP0419760B1 Zero standby power, radiation hardened, memory redundancy circuit
08/21/1996CN1129338A Semi-conductor memory element
08/20/1996US5548743 Data processing system with duplex common memory having physical and logical path disconnection upon failure
08/20/1996US5548720 Fault supervision method for transmission apparatus
08/20/1996US5548716 Recording medium dualizing system
08/20/1996US5548596 Semiconductor memory device with read out data transmission bus for simultaneously testing a plurality of memory cells and testing method thereof
08/20/1996US5548557 Nonvolatile semiconductor memory device with a row redundancy circuit
08/20/1996US5548555 Method and circuit for repairing defect in a semiconductor memory device
08/20/1996US5548554 Integrated programming circuitry for an electrically programmable semiconductor memory device with redundancy
08/20/1996US5548553 Method and apparatus for providing high-speed column redundancy
08/20/1996US5548225 Block specific spare circuit
08/15/1996WO1996024898A1 Apparatus for entering and executing test mode operations for memory
08/15/1996WO1996024897A2 Parallel processing redundancy scheme for faster access times and lower die area
08/15/1996WO1996011472A3 A memory device
08/14/1996EP0726521A2 Disk array having hot spare resources and methods for using hot spare resources to store user data
08/14/1996EP0726514A2 Methods for using non contiguously reserved storage space for data migration in a redundant hierarchic data storage system
08/13/1996US5546558 Memory system with hierarchic disk array and memory map store for persistent storage of virtual mapping information
08/13/1996US5546556 Disk storage system have a defect map of the disk stored in a memory which is different from the disk
08/13/1996US5546537 Method and apparatus for parallel testing of memory
08/13/1996US5546410 Semiconductor memory device with error self-correction system starting parity bit generation/error correction sequences only when increase of error rate is forecasted
08/13/1996US5546407 Data transmission circuit for checking of memory device
08/13/1996US5546402 Flash-erase-type nonvolatile semiconductor storage device
08/13/1996US5546351 Non-volatile semiconductor memory device and memory system using the same
08/13/1996US5546349 Exchangeable hierarchical data line structure
08/13/1996US5546348 Semiconductor disc storage
08/08/1996WO1996024135A1 Memory having adjustable operating characteristics and methods therefor
08/07/1996EP0725344A1 Semiconductor device incorporating fuse-type roll call circuit
08/07/1996EP0725324A2 Methods for avoiding overcommitment of virtual capacity in a redundant hierarchic data storage system
08/06/1996US5544341 Data access apparatus for preventing further cache access in case of an error during block data transfer
08/06/1996US5544339 Array of disk drives with redundant channels
08/06/1996US5544312 Method of detecting loss of power during block erasure and while writing sector data to a solid state disk
08/06/1996US5544175 Method and apparatus for the capturing and characterization of high-speed digital information
08/06/1996US5544123 Semiconductor memory device having a test circuit
08/06/1996US5544118 Flash EEPROM system cell array with defect management including an error correction scheme
08/06/1996US5544116 Erase and program verification circuit for non-volatile memory
08/06/1996US5544113 Random access memory having a flexible array redundancy scheme
08/06/1996US5544108 Monolithic memory device
08/06/1996US5544107 Diagnostic data port for a LSI or VLSI integrated circuit
08/06/1996US5544106 Semiconductor memory device with redundant decoder available for test sequence on redundant memory cells
08/06/1996US5544105 Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing
08/06/1996US5544098 Semiconductor memory device having an automatically activated verify function capability
08/01/1996WO1996023259A1 Fault tolerant nfs server system and mirroring protocol
08/01/1996DE19602814A1 Non-volatile semiconductor read-only memory with row redundancy
07/1996
07/31/1996EP0724267A1 Programmable multibit register for coincidence and jump operations and coincidence fuse cell
07/30/1996US5542066 Destaging modified data blocks from cache memory
07/30/1996US5542065 Methods for using non-contiguously reserved storage space for data migration in a redundant hierarchic data storage system
07/30/1996US5542064 Data read/write method by suitably selecting storage units in which multiple copies of identical data are stored and apparatus therefor
07/30/1996US5541942 Method and system for testing memory utilizing specific bit patterns
07/30/1996US5541938 Method and apparatus for mapping memory as to operable and faulty locations
07/30/1996US5541887 Multiple port cells with improved testability
07/25/1996WO1996022569A1 Self-diagnostic asynchronous data buffers
07/25/1996DE19600804A1 Internal voltage generator circuit for semiconductor memory e.g. DRAM
07/25/1996CA2210153A1 Self-diagnostic asynchronous data buffers
07/24/1996EP0723262A2 scanning memory device and error correction method
07/24/1996EP0722609A1 Circuitry and method for selecting a drain programming voltage for a nonvolatile memory
07/23/1996US5539878 Parallel testing of CPU cache and instruction units
07/23/1996US5539753 Method and apparatus for output deselecting of data during test
07/23/1996US5539702 Test apparatus for semi-conductor memory device
07/23/1996US5539699 Flash memory testing apparatus
07/23/1996US5539698 For replacing a defective normal memory cell with a spare one
07/23/1996US5539697 Method and structure for using defective unrepairable semiconductor memory
07/23/1996US5539694 Memory with on-chip detection of bit line leaks