| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
|---|
| 02/05/1998 | WO1998005037A1 Semiconductor storage device |
| 02/04/1998 | EP0822496A2 Fuse refresh circuit |
| 02/03/1998 | US5715253 ROM repair circuit |
| 02/03/1998 | US5715202 Semiconductor memory device |
| 02/03/1998 | US5715193 Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks |
| 02/03/1998 | US5715188 Method and apparatus for parallel addressing of CAMs and RAMs |
| 01/29/1998 | WO1998003979A1 Semiconductor memory tester with redundancy analysis |
| 01/29/1998 | WO1998003915A2 Flash memory card |
| 01/29/1998 | DE4336883C2 Ausgangstreiberschaltung Output driver circuit |
| 01/28/1998 | EP0820631A1 Circuit for sram test mode isolated bitline modulation |
| 01/28/1998 | EP0654739B1 Automatic repair data editing system associated with repairing system for semiconductor integrated circuit device |
| 01/28/1998 | CN1171855A 存储器设备 Memory device |
| 01/27/1998 | US5712859 Semiconductor integrated circuit |
| 01/27/1998 | US5712822 Microprocessor memory test circuit and method |
| 01/27/1998 | US5712821 Redundancy circuit of semiconductor memory device |
| 01/27/1998 | US5712819 Flash EEPROM system with storage of sector characteristic information within the sector |
| 01/27/1998 | US5712816 Method for evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories |
| 01/27/1998 | US5712588 Fuse element for a semiconductor memory device |
| 01/27/1998 | US5712584 Synchronous stress test control |
| 01/22/1998 | WO1998002887A1 Method and device for quantifying the impact of cosmic radiation on an electronic equipement with memory |
| 01/22/1998 | WO1998002816A1 Block erasable memory system defect handling |
| 01/21/1998 | EP0819276A1 Memory management |
| 01/21/1998 | EP0819275A1 Method and system for testing memory programming devices |
| 01/21/1998 | EP0469252B1 Laser link decoder for DRAM redundancy scheme |
| 01/21/1998 | CN1170936A Semiconductor integrated circuit having test circuit |
| 01/20/1998 | US5710778 High voltage reference and measurement circuit for verifying a programmable cell |
| 01/20/1998 | US5710737 Semiconductor memory device |
| 01/20/1998 | US5710734 Semiconductor memory device and data writing method thereof |
| 01/14/1998 | EP0817998A1 Memory testing in a multiple processor computer system |
| 01/14/1998 | CN1170161A Renumbered array architecture for multi-array memories |
| 01/13/1998 | US5708791 System and method for detecting the DRAM architecture in a computer |
| 01/13/1998 | US5708789 Structure to utilize a partially functional cache memory by invalidation of faulty cache memory locations |
| 01/13/1998 | US5708771 Fault tolerant controller system and method |
| 01/13/1998 | US5708668 Method and apparatus for operating an array of storage devices |
| 01/13/1998 | US5708619 Column redundancy scheme for DRAM using normal and redundant column decoders programmed with defective array address and defective column address |
| 01/13/1998 | US5708614 Data output control circuit of semiconductor memory device having pipeline structure |
| 01/13/1998 | US5708613 For use in computer systems |
| 01/13/1998 | US5708612 Semiconductor memory device |
| 01/13/1998 | US5708606 Semiconductor memory device and high-voltage switching circuit |
| 01/13/1998 | US5708601 Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device |
| 01/07/1998 | EP0817202A2 Testing of a semi-conductor integrated circuit device |
| 01/07/1998 | EP0817057A2 Method and apparatus for efficient self testing of on-chip memory |
| 01/07/1998 | EP0817054A2 Simultaneous, mirror write cache |
| 01/07/1998 | EP0721645A4 Automatic test circuitry with non-volatile status write |
| 01/07/1998 | CN1169560A Logical check apparatus for semiconductor circuits |
| 01/06/1998 | US5706468 Method and apparatus for monitoring and interfacing a dual port random access memory in a system having at least two independent CPUs |
| 01/06/1998 | US5706424 System for fast read and verification of microcode RAM |
| 01/06/1998 | US5706423 Data processor having data bus and instruction fetch bus provided separately from each other |
| 01/06/1998 | US5706293 Method of testing single-order address memory |
| 01/06/1998 | US5706292 Layout for a semiconductor memory device having redundant elements |
| 01/06/1998 | US5706237 Self-restore circuit with soft error protection for dynamic logic circuits |
| 01/06/1998 | US5706235 Memory circuit with switch for selectively connecting an I/O pad directly to a nonvolatile memory cell and method for operating same |
| 01/06/1998 | US5706234 Testing and repair of wide I/O semiconductor memory devices designed for testing |
| 01/06/1998 | US5706233 Semiconductor memory device allowing acceleration testing, and a semi-finished product for an integrated semiconductor device that allows acceleration testing |
| 01/06/1998 | US5706232 Semiconductor memory with multiple clocking for test mode entry |
| 01/06/1998 | US5706231 Semiconductor memory device having a redundant memory cell |
| 01/06/1998 | US5706032 Amendable static random access memory |
| 01/06/1998 | US5705934 Integrated circuit |
| 01/06/1998 | US5704489 SIMM/DIMM board handler |
| 01/02/1998 | DE19726837A1 Storage test system for testing semiconductor memory unit |
| 01/02/1998 | DE19625626A1 Data storage control method for faulty memory |
| 12/31/1997 | CN1169016A Semi-conductor storage device |
| 12/31/1997 | CN1168999A Method and apparatus for detecting and concealing data errors in stored digital data |
| 12/30/1997 | US5704035 Computer method/apparatus for performing a basic input/output system (BIOS) power on test (POST) that uses three data patterns and variable granularity |
| 12/30/1997 | US5704033 Apparatus and method for testing a program memory for a one-chip microcomputer |
| 12/30/1997 | US5703888 Method for checking a reloadable memory, memory checking device, and automatic data restoring device |
| 12/30/1997 | US5703824 Semiconductor memory device |
| 12/30/1997 | US5703823 Data processing system |
| 12/30/1997 | US5703818 Test circuit |
| 12/30/1997 | US5703817 Semiconductor memory device |
| 12/30/1997 | US5703816 Failed memory cell repair circuit of semiconductor memory |
| 12/30/1997 | US5703495 Data output impedance control |
| 12/29/1997 | EP0813711A1 Error management processes for flash eeprom memory arrays |
| 12/23/1997 | US5701492 Fail-safe flashing of EPROM |
| 12/23/1997 | US5701436 Information processing apparatus including synchronous storage having backup registers for storing the latest sets of information to enable state restoration after interruption |
| 12/23/1997 | US5701431 Method and system for randomly selecting a cache set for cache fill operations |
| 12/23/1997 | US5701335 Frequency independent scan chain |
| 12/23/1997 | US5701270 Single chip controller-memory device with interbank cell replacement capability and a memory architecture and methods suitble for implementing the same |
| 12/23/1997 | US5701267 Semiconductor storage device with macro-cell with monitoring of input data |
| 12/23/1997 | US5700698 Method for screening non-volatile memory and programmable logic devices |
| 12/17/1997 | EP0813209A2 Method for erasing non-volatile memory |
| 12/16/1997 | US5699510 Failure detection system for a mirrored memory dual controller disk storage system |
| 12/16/1997 | US5699509 Method and system for using inverted data to detect corrupt data |
| 12/16/1997 | US5699508 Keyboard testing methods and apparatus |
| 12/16/1997 | US5699308 Semiconductor memory device having two layers of bit lines arranged crossing with each other |
| 12/16/1997 | US5699307 Method and apparatus for providing redundant memory in an integrated circuit utilizing a subarray shuffle replacement scheme |
| 12/16/1997 | US5699306 Row redundancy for nonvolatile semiconductor memories |
| 12/16/1997 | US5699296 Threshold voltage verification circuit of a non-volatile memory cell and program and erasure verification method using the same |
| 12/16/1997 | US5698876 Memory standard cell macro for semiconductor device |
| 12/11/1997 | WO1997046942A1 Redundancy concept for memory circuits with rom storage cells |
| 12/11/1997 | DE19723434A1 Testing apparatus for semiconductors in integrated circuits |
| 12/10/1997 | EP0811989A2 A method and apparatus for testing an integrated circuit memory array |
| 12/10/1997 | EP0811988A1 Semiconductor memory device with row and column redundancy circuits and a time-shared redundancy circuit test architecture |
| 12/10/1997 | EP0811919A1 Memory device with clocked column redundancy |
| 12/10/1997 | EP0811918A1 Semiconductor memory device with clocked column redundancy and time-shared redundancy data transfer approach |
| 12/10/1997 | EP0811917A1 Circuit for transferring redundancy data of a redundancy circuit inside a memory device by means of a time-shared approach |
| 12/10/1997 | EP0641485A4 Membrane dielectric isolation ic fabrication. |
| 12/10/1997 | EP0523973B1 A configurable self-test for embedded RAMs |
| 12/09/1997 | US5696943 Method and apparatus for quick and reliable design modification on silicon |
| 12/09/1997 | US5696934 Method of utilizing storage disks of differing capacity in a single storage volume in a hierarchial disk array |