Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
12/1997
12/09/1997US5696770 Method and apparatus for testing circuitry with memory and with forcing circuitry
12/09/1997US5696723 Defect relief decision circuit with dual-fused clocked inverter
12/09/1997US5696716 Programmable memory element
12/04/1997WO1997045872A1 Method and apparatus for programming anti-fuses using internally generated programming voltage
12/04/1997DE19722414A1 Method and device for testing semiconductor interference analysis memory
12/04/1997DE19622275A1 Redundanzkonzept für integrierte Speicher mit ROM-Speicherzellen Redundancy concept for integrated memory ROM memory cells
12/04/1997DE19621875A1 System testing equipment for mine laying vehicle
12/03/1997EP0809849A1 On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same
12/02/1997US5694611 Microcomputer including internal and direct external control of EEPROM and method of making the microcomputer
12/02/1997US5694400 Checking data integrity in buffered data transmission
12/02/1997US5694368 Memory device with efficient redundancy using sense amplifiers
12/02/1997US5694364 Semiconductor integrated circuit device having a test mode for reliability evaluation
12/02/1997US5694359 Flash memory device
11/1997
11/27/1997DE19721310A1 Semiconductor memory chip repair on wafer
11/26/1997EP0809186A2 Method and apparatus of redundancy for non-volatile memory integrated circuits
11/26/1997EP0809185A1 A shared storage duplicating method
11/26/1997EP0808487A1 Apparatus for entering and executing test mode operations for memory
11/26/1997EP0808486A2 Parallel processing redundancy scheme for faster access times and lower die area
11/25/1997US5692187 Shadow mechanism having masterblocks for a modifiable object oriented system
11/25/1997US5691952 Semiconductor memory device and memory module using the same
11/25/1997US5691951 Row decoder circuit in a memory integrated circuit
11/25/1997US5691949 Very high density wafer scale device architecture
11/25/1997US5691946 Row redundancy block architecture
11/25/1997US5691945 Technique for reconfiguring a high density memory
11/20/1997WO1997043713A1 Substitute memory timing circuit
11/20/1997DE19714952A1 Verwaltung von Speichermodulen Management of memory modules
11/19/1997EP0471540B1 A semiconductor memory with a flag for indicating test mode
11/18/1997US5689729 Storage subsystem having plurality of access paths permitting independent access to cache memory from host and independent access to the cache from rotating storage device
11/18/1997US5689635 Microprocessor memory test circuit and method
11/18/1997US5689634 Three purpose shadow register attached to the output of storage devices
11/18/1997US5689514 Method and apparatus for testing the address system of a memory system
11/18/1997US5689469 Semiconductor memory devices
11/18/1997US5689467 Apparatus and method for reducing test time of the data retention parameter in a dynamic random access memory
11/18/1997US5689466 Built in self test (BIST) for multiple RAMs
11/18/1997US5689465 Semiconductor memory device and defective memory cell correction circuit
11/18/1997US5689464 Column repair circuit for integrated circuits
11/18/1997US5689463 Semiconductor memory device
11/13/1997WO1997042515A1 Methods and systems for increased numbers of test points on printed circuit boards
11/13/1997CA2253336A1 Methods and systems for increased numbers of test points on printed circuit boards
11/12/1997EP0806773A1 Electrically erasable and programmable non-volatile memory device with testable redundancy circuits
11/12/1997EP0806727A2 TFT/LCD active data line repair
11/12/1997EP0806010A1 Fault tolerant nfs server system and mirroring protocol
11/12/1997EP0664029B1 Computer failure recovery and alert system
11/12/1997EP0528280B1 Memory card apparatus
11/12/1997EP0514164B1 Efficiency improved DRAM row redundancy circuit
11/11/1997US5687179 Serial data input/output method and apparatus
11/11/1997US5687178 Method and apparatus for testing a static RAM
11/11/1997US5687125 Semiconductor memory device having redundancy memory cells incorporated into sub memory cell blocks
11/05/1997EP0805460A1 Integrated circuit having a built-in selft-test arrangement
11/05/1997EP0805459A1 Method and apparatus for testing DRAM memory units
11/05/1997EP0805451A2 Integrated circuit memory using fusible links in a scan chain
11/05/1997EP0804762A1 Self-diagnostic asynchronous data buffers
11/05/1997CN1164129A Semiconductor memory devices
11/04/1997US5684979 Method and means for initializing a page mode memory in a computer
11/04/1997US5684944 Atomic update of EDC protected data
11/04/1997US5684809 Semiconductor memory with test circuit
11/04/1997US5684748 Circuit for testing reliability of chip and semiconductor memory device having the circuit
11/04/1997US5684747 Method for erasing nonvolatile semiconductor memory device incorporating redundancy memory cells
11/04/1997US5684746 Semiconductor memory device in which a failed memory cell is placed with another memory cell
11/04/1997US5684740 Semiconductor memory and method for substituting a redundancy memory cell
10/1997
10/30/1997WO1997040444A1 Layout for a semiconductor memory device having redundant elements
10/30/1997DE19716366A1 Pattern generator for semiconductor testing system
10/30/1997DE19713421A1 Semiconductor memory test apparatus with memory unit for DRAM
10/30/1997DE19531683C2 Flash-Speicher mit Datenauffrischfunktion und Datenauffrischverfahren eines Flash-Speichers Flash memory with Datenauffrischfunktion and Datenauffrischverfahren a flash memory
10/29/1997EP0803902A2 Semiconductor device with on-board memory areas for test purposes
10/29/1997CN1163475A Mixed packing semiconductor integrate circuit device of controller mass storage and measuring method
10/28/1997USRE35645 Semiconductor memory device having a test mode setting circuit
10/28/1997US5682472 Semiconductor device testing apparatus
10/28/1997US5682393 For adjusting a delay time of a memory device to be tested
10/28/1997US5682390 Pattern generator in semiconductor test system
10/28/1997US5682389 Non-volatile memory device having built-in test pattern generator used in a diagnostic operation on control signal lines for data propagation path
10/28/1997US5682352 Integrated circuit
10/28/1997US5682349 Failure tolerant memory device, in particular of the flash EEPROM type
10/23/1997DE19610123C1 Burn-in-board and electrical component testing method
10/22/1997EP0802541A1 Method for detecting redundant defective addresses in a memory device with redundancy
10/22/1997EP0802483A1 Semiconductor memory device with row redundancy
10/22/1997EP0802482A1 Redundancy memory register
10/22/1997CN1162820A Signal generator
10/22/1997CN1162817A Semiconductor memory
10/21/1997US5680579 Redundant array of solid state memory devices
10/21/1997US5680570 Memory system with dynamically allocatable non-volatile storage capability
10/21/1997US5680544 For testing a random access memory
10/21/1997US5680362 Circuit and method for accessing memory cells of a memory device
10/21/1997US5680354 Semiconductor memory device capable of reading information stored in a non-volatile manner in a particular operation mode
10/15/1997EP0801401A1 Testing and repair of embedded memory
10/15/1997EP0801400A1 Testing and repair of embedded memory
10/15/1997CN1162150A Data protection circuit
10/14/1997US5678061 Method for employing doubly striped mirroring of data and reassigning data streams scheduled to be supplied by failed disk to respective ones of remaining disks
10/14/1997US5677917 Integrated circuit memory using fusible links in a scan chain
10/14/1997US5677913 Method and apparatus for efficient self testing of on-chip memory
10/14/1997US5677888 Redundancy circuit for programmable integrated circuits
10/14/1997US5677887 Semiconductor memory device having a large storage capacity and a high speed operation
10/14/1997US5677885 Memory system with non-volatile data storage unit and method of initializing same
10/14/1997US5677884 Integrated circuit memory array
10/14/1997US5677883 Semiconductor associative memory device with address corrector for generating formal address signal representative of one of regular memory words partially replaced with redundant memory word
10/14/1997US5677882 Semiconductor memory having redundancy memory decoder circuit
10/14/1997US5677881 Semiconductor memory device having a shortened test time and contol method therefor
10/14/1997US5677880 Semiconductor memory having redundancy circuit
10/14/1997US5677879 Method and apparatus for performing memory cell verification on a nonvolatile memory circuit
10/14/1997US5677877 Integrated circuit chips with multiplexed input/output pads and methods of operating same