G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation

Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/1998
11/17/1998	US5838620 Method of repairing an integrated circuit
11/17/1998	US5838619 Method and apparatus for redundancy management of non-volatile memories
11/17/1998	US5838614 Identification and verification of a sector within a block of mass storage flash memory
11/17/1998	US5838163 Testing and exercising individual, unsingulated dies on a wafer
11/17/1998	US5838022 Evaluating the lifetime and reliability of a TFT in a stress test using gate voltage and temperature measurements
11/17/1998	CA2045948C Data file directories and methods
11/12/1998	WO1998050857A1 Programmable universal test interface and method for making the same
11/12/1998	DE19820442A1 Memory testing method for customer final check
11/11/1998	EP0655164B1 Self-testing device for storage arrangements, decoders or the like
11/11/1998	EP0621537B1 Structure to recover a portion of a partially functional embedded memory
11/11/1998	CN1040707C Semiconductor memory device having improved redundancy efficiency
11/10/1998	US5835969 Address test pattern generator for burst transfer operation of a SDRAM
11/10/1998	US5835963 Processor with an addressable address translation buffer operative in associative and non-associative modes
11/10/1998	US5835927 Special test modes for a page buffer shared resource in a memory device
11/10/1998	US5835704 Microprocessor system
11/10/1998	US5835695 Method for a primary BIOS ROM recovery in a dual BIOS ROM computer system
11/10/1998	US5835504 In a built-in self test of a processor
11/10/1998	US5835503 Method for programming an integrated circuit device
11/10/1998	US5835502 Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme
11/10/1998	US5835445 Semiconductor integrated circuit device having a synchronous output function with a plurality of external clocks
11/10/1998	US5835434 Internal voltage generating circuit, semiconductor memory device, and method of measuring current consumption, capable of measuring current consumption without cutting wire
11/10/1998	US5835431 Method and apparatus for wafer test of redundant circuitry
11/10/1998	US5835430 Method of providing redundancy in electrically alterable memories
11/10/1998	US5835429 In a static random access memory
11/10/1998	US5835428 Method of testing semiconductor memory and apparatus for carrying out the method
11/10/1998	US5835427 Method of stressing an integrated circuit memory device
11/10/1998	US5835426 Redundant circuit
11/10/1998	US5835425 Repairable semiconductor memory array
11/10/1998	US5835424 Semiconductor memory
11/10/1998	US5835419 Semiconductor memory device with clamping circuit for preventing malfunction
11/10/1998	US5835416 Flash-erasable semiconductor memory device having an improved reliability
11/10/1998	US5835415 Flash EEPROM memory systems and methods of using them
11/10/1998	US5835408 Flash-erasable semiconductor memory device having an improved reliability
11/10/1998	US5835407 Flash memory device
11/10/1998	US5834970 In an integrated circuit
11/10/1998	US5834334 Method of forming a multi-chip module from a membrane circuit
11/04/1998	EP0757837B1 A method and apparatus for testing a memory circuit with parallel block write operation
11/04/1998	EP0548564B1 Storage device employing a flash memory
11/04/1998	CN1197986A Semiconductor memory device with redundancy circuit
11/03/1998	US5832486 Distributed database system having master and member sub-systems connected through a network
11/03/1998	US5831989 Memory testing apparatus
11/03/1998	US5831988 Fault isolating to a block of ROM
11/03/1998	US5831987 Method for testing cache memory systems
11/03/1998	US5831986 Method of testing a circuit
11/03/1998	US5831933 Programmable semiconductor memory device
11/03/1998	US5831923 Antifuse detect circuit
11/03/1998	US5831918 Circuit and method for varying a period of an internal control signal during a test mode
11/03/1998	US5831917 Techniques for reducing redundant element fuses in a dynamic random access memory array
11/03/1998	US5831916 Method for replacing defective elements of a memory array
11/03/1998	US5831915 Memory device with clocked column redundancy
11/03/1998	US5831914 Variable size redundancy replacement architecture to make a memory fault-tolerant
11/03/1998	US5831913 Method of making a memory fault-tolerant using a variable size redundancy replacement configuration
11/03/1998	US5831903 Electrically erasable programmable read-only memory with threshold value controller for data programming and method of programming the same
11/03/1998	US5831856 DRAM testing apparatus
11/03/1998	US5831467 Termination circuit with power-down mode for use in circuit module architecture
10/1998
10/29/1998	DE19754899A1 Automatic refresh control circuit for semiconductor apparatus
10/28/1998	EP0874370A1 Sense amplifier control of a memory device
10/28/1998	EP0554053B1 A semiconductor memory with a multiplexer for selecting an output for a redundant memory access
10/28/1998	EP0525680B1 Data latch circuit having non-volatile memory cell
10/27/1998	US5829030 System for performing cache flush transactions from interconnected processor modules to paired memory modules
10/27/1998	US5829015 Semiconductor integrated circuit device having multi-port RAM memory with random logic portion which can be tested without additional test circuitry
10/27/1998	US5828826 Processing apparatus having a nonvolatile memory to which a supply voltage is supplied through a shared terminal
10/27/1998	US5828825 Method and apparatus for pseudo-direct access to embedded memories of a micro-controller integrated circuit via the IEEE test access port
10/27/1998	US5828820 Mirror disk control method and mirror disk device
10/27/1998	US5828673 Logical check apparatus and method for semiconductor circuits and storage medium storing logical check program for semiconductor circuits
10/27/1998	US5828624 Decoder circuit and method for disabling a number of columns or rows in a memory
10/27/1998	US5828621 Semiconductor memory device and high-voltage switching circuit
10/27/1998	US5828599 Memory with electrically erasable and programmable redundancy
10/27/1998	US5828592 Analog signal recording and playback integrated circuit and message management system
10/27/1998	US5828258 Semiconductor device and testing apparatus thereof
10/27/1998	US5828229 Programmable logic array integrated circuits
10/22/1998	WO1998047152A1 Semiconductor integrated circuit and method for testing memory
10/22/1998	WO1998047060A2 Systems and methods for protecting access to encrypted information
10/22/1998	WO1998034220A3 Method and apparatus for verifying erasure of memory blocks within a non-volatile memory structure
10/22/1998	DE4105104C3 Halbleiterspeichereinrichtung und Verfahren zur Fehlerkorrektur A semiconductor memory device and method for error correction
10/21/1998	EP0553788B1 Semiconductor memory device incorporating redundancy memory cells having parallel test function
10/21/1998	CN1196838A Zero-power fuse circuit
10/20/1998	US5826007 Memory data protection circuit
10/20/1998	US5826006 Method and apparatus for testing the data output system of a memory system
10/20/1998	US5825783 Semiconductor integrated circuit device with large-scale memory and controller embedded on one semiconductor chip and method of testing the device
10/20/1998	US5825782 Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns
10/20/1998	US5825712 Semiconductor integrated circuit
10/20/1998	US5825700 Low voltage test mode operation enable scheme with hardware safeguard
10/20/1998	US5825699 Semiconductor memory device fixing defective memory cell selection line replaced with spare memory cell selection line in non-selected state
10/20/1998	US5825698 Redundancy decoding circuit for a semiconductor memory device
10/20/1998	US5825697 Circuit and method for enabling a function in a multiple memory device module
10/20/1998	US5825694 Semiconductor memory device capable of preventing malfunction due to disconnection of column select line or word select line
10/20/1998	US5825682 Cache memory capable of using faulty tag memory
10/15/1998	WO1998045850A1 A ram-like test structure superimposed over rows of macrocells with added differential pass transistors in a cpu
10/14/1998	EP0871179A1 Test method and circuit for semiconductor memory
10/14/1998	EP0871124A2 A fuseless memory repair system and method of operation
10/14/1998	EP0819275A4 Method and system for testing memory programming devices
10/14/1998	CN1195891A Semiconductor integrated circuit and method of testing synchronous dynamic random memory core
10/14/1998	CN1195866A Semiconductor memory device
10/14/1998	CN1195848A Memory read method and circuit for error checking and correction in decoding device
10/14/1998	CN1195815A Method of making memory fault-tolerant using variable size redundancy replacement configuration
10/14/1998	CN1195814A Variable size redundancy replacement architecture to make memory fault-tolerant
10/13/1998	US5822777 Dual bus data storage system having an addressable memory with timer controller fault detection of data transfer between the memory and the buses
10/13/1998	US5822516 Enhanced test method for an application-specific memory scheme
10/13/1998	US5822334 High speed initialization system for RAM devices using JTAG loop for providing valid parity bits

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