Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/1999
11/02/1999US5978949 Failure analysis device for IC tester and memory device measuring device for IC tester
11/02/1999US5978946 Methods and apparatus for system testing of processors and computers using signature analysis
11/02/1999US5978945 Tester arrangement comprising a connection module for testing, by way of the boundary scan test method, a carrier provided with a first number of digital ICS with BST logic and a second number of digital ICS without BST logic
11/02/1999US5978941 Semiconductor memory device having deterioration determining function
11/02/1999US5978935 Method for built-in self-testing of ring-address FIFOs having a data input register with transparent latches
11/02/1999US5978931 Variable domain redundancy replacement configuration for a memory device
11/02/1999US5978565 Method for rapid recovery from a network file server failure including method for operating co-standby servers
11/02/1999US5978306 Memory device having a redundant memory block
11/02/1999US5978298 Shared pull-up and selection circuitry for programmable cells such as antifuse cells
11/02/1999US5978297 Method and apparatus for strobing antifuse circuits in a memory device
11/02/1999US5978294 Memory cell evaluation semiconductor device, method of fabricating the same and memory cell evaluation method
11/02/1999US5978292 Consumption current circuit and method for memory device
11/02/1999US5978291 Sub-block redundancy replacement for a giga-bit scale DRAM
11/02/1999US5978290 Semiconductor memory device
11/02/1999US5978289 Apparatus for testing redundant elements in a packaged semiconductor memory device
10/1999
10/28/1999WO1999054819A1 Storage device with redundant storage cells and method for accessing redundant storage cells
10/28/1999WO1999037083A3 Affine transformation means and method of affine transformation
10/28/1999DE19917085A1 Address decoder switch for external macros, providing test mode
10/28/1999DE19833208C1 Integrated circuit with built-in self-test device
10/27/1999EP0952525A1 Ic card
10/27/1999EP0856188B1 A flash eeprom memory with separate reference array
10/27/1999EP0543712B1 Integrated memory, method of control and resulting information system
10/27/1999CN1233060A Semiconductor memory device
10/27/1999CN1233059A Memory test device and method capable of achieving fast memory test without increasing chip pin number
10/27/1999CN1233053A Error correction apparatus
10/26/1999US5974579 Efficient built-in self test for embedded memories with differing address spaces
10/26/1999US5974564 Method for remapping defective memory bit sets to non-defective memory bit sets
10/26/1999US5974510 Method for testing the non-cacheable region functioning of a cache memory controller
10/26/1999US5974506 Enabling mirror, nonmirror and partial mirror cache modes in a dual cache system
10/26/1999US5973990 Synchronous semiconductor memory device including a circuit for arbitrarily controlling activation/inactivation timing of word line
10/26/1999US5973981 Stress test apparatus and method for semiconductor memory device
10/26/1999US5973971 Device and method for verifying independent reads and writes in a memory array
10/26/1999US5973970 Semiconductor memory device incorporating redundancy memory cells having uniform layout
10/26/1999US5973969 Defective memory cell address detecting circuit
10/26/1999US5973964 Flash memory control method and information processing system therewith
10/26/1999US5973340 Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits
10/26/1999US5971606 Module and apparatus for measuring temperature properties of an SRAM IC
10/21/1999WO1999044752A3 Circuit and method for specifying performance parameters in integrated circuits
10/21/1999DE19916903A1 Adjustment of delay time in computer processes
10/21/1999DE19912467A1 Editing apparatus for definition of a physical translation of logic result bit map into physical result bit map
10/21/1999DE19900299A1 Memory tester with output of data pertaining to test sample
10/20/1999CN1232273A Reduced signal test for dynamic random access memory
10/20/1999CN1232263A Information recording method and apparatus
10/20/1999CN1232186A Address decoding circuit and method of address decoding
10/19/1999US5970016 Dynamic semiconductor memory device with banks capable of operating independently
10/19/1999US5970015 Semiconductor integrated circuit device allowing change of product specification and chip screening method therewith
10/19/1999US5970013 Adaptive addressable circuit redundancy method and apparatus with broadcast write
10/19/1999US5970011 Power source design for embedded memory
10/19/1999US5970008 Efficient method for obtaining usable parts from a partially good memory integrated circuit
10/19/1999US5970004 Semiconductor memory device allowing test regardless of spare cell arrangement
10/19/1999US5970003 Semiconductor memory device
10/19/1999US5970002 Semiconductor memory device having redundancy function
10/19/1999US5970001 Dynamic RAM provided with a defect relief circuit
10/19/1999US5970000 Repairable semiconductor integrated circuit memory by selective assignment of groups of redundancy elements to domains
10/19/1999US5968192 Programmable universal test interface and method for making the same
10/19/1999US5968190 Redundancy method and circuit for self-repairing memory arrays
10/19/1999US5968183 Semiconductor memory device with clocked column redundancy and time-shared redundancy data transfer approach
10/19/1999US5968181 One-chip clock synchronized memory device
10/13/1999EP0948793A1 High-speed test system for a memory device
10/13/1999EP0565079B1 Semiconductor device including voltage stress test shunting circuit
10/13/1999CN1231482A Semiconductor IC device with internal testing circuit
10/13/1999CN1231481A Multivalue semiconductor memory device and error erasing method thereof
10/13/1999CN1045675C Fault tolerant queue system
10/12/1999US5966389 Flexible ECC/parity bit architecture
10/12/1999US5966388 Semiconductor memory device
10/12/1999US5966339 Programmable/reprogrammable fuse
10/12/1999US5966336 Semiconductor device having redundancy circuit
10/12/1999US5966335 Semiconductor memory device having circuit for changing electrical characteristics
10/12/1999US5966334 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
10/12/1999US5966333 Semiconductor memory device
10/12/1999US5966330 In a semiconductor integrated circuit memory device
10/12/1999US5966025 Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device
10/12/1999US5966021 Apparatus for testing an integrated circuit in an oven during burn-in
10/12/1999US5965902 Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device
10/12/1999US5964884 Self-timed pulse control circuit
10/07/1999WO1999050748A1 Memory system
10/07/1999WO1999044113A3 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
10/06/1999EP0947995A2 Weak bit testing
10/06/1999EP0947994A2 Reduced signal test for dynamic random access memory
10/06/1999EP0946988A1 Memory redundancy circuit using single polysilicon floating gate transistors as redundancy elements
10/06/1999EP0845122B1 Memory tester providing fast repair of memory chips
10/06/1999EP0581309B1 Burn-in test enable circuit of a semiconductor memory device and burn-in test method
10/05/1999USRE36325 Directly bonded SIMM module
10/05/1999US5963976 System for configuring a duplex shared storage
10/05/1999US5963970 Method and apparatus for tracking erase cycles utilizing active and inactive wear bar blocks having first and second count fields
10/05/1999US5963566 Application specific integrated circuit chip and method of testing same
10/05/1999US5963500 Semiconductor memory device
10/05/1999US5963492 For use in a memory chip
10/05/1999US5963491 Semiconductor memory
10/05/1999US5963490 Static semiconductor memory device having a variable power supply voltage applied to a memory cell depending on the state in use and method of testing the same
10/05/1999US5963489 Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device
10/05/1999US5963488 Semiconductor memory device
10/05/1999US5963480 Highly compact EPROM and flash EEPROM devices
10/05/1999US5963474 Secondary storage device using nonvolatile semiconductor memory
10/05/1999US5963473 Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks
10/05/1999US5962868 Semiconductor device having contact check circuit
10/05/1999US5961657 Parallel test circuit for semiconductor memory device
10/05/1999US5961653 Processor based BIST for an embedded memory
09/1999
09/30/1999DE19912417A1 Integrated circuit test device for semiconductor elements
09/30/1999DE19813504A1 Circuit arrangement for automatic detection and removal of word-line and bit-line short circuits