G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation

Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/1999
11/30/1999	US5995731 Multiple BIST controllers for testing multiple embedded memory arrays
11/30/1999	US5995443 Synchronous memory device
11/30/1999	US5995429 Semiconductor memory device capable of multiple word-line selection and method of testing same
11/30/1999	US5995428 Circuit for burn-in operation on a wafer of memory devices
11/30/1999	US5995427 Semiconductor memory device having test mode
11/30/1999	US5995426 Testing parameters of an electronic device
11/30/1999	US5995424 Synchronous memory test system
11/30/1999	US5995423 Method and apparatus for limiting bitline current
11/30/1999	US5995422 Redundancy circuit and method of a semiconductor memory device
11/30/1999	US5995413 Trimbit circuit for flash memory integrated circuits
11/25/1999	WO1999060618A1 Semiconductor device and method of manufacture thereof
11/25/1999	DE19921756A1 Memory tester with data-selecting circuit for packet system storage components
11/25/1999	DE19903606A1 Memory sense circuit operated by selected delays
11/24/1999	EP0958562A1 Occupancy sensor and method of operating same
11/24/1999	EP0760155B1 A single chip controller-memory device and a memory architecture and methods suitable for implementing the same
11/24/1999	CN1236452A Method of updating program code for an optical disc drive microcontroller and an optical disc drive
11/24/1999	CN1236172A Apparatus for redundant treatment in semiconductor memory chip
11/24/1999	CN1236170A Semiconductor device, and method of designing semiconductor device
11/23/1999	US5991905 Process and device for testing a memory element
11/23/1999	US5991904 Method and apparatus for rapidly testing memory devices
11/23/1999	US5991903 Parallel bit test circuit for testing a semiconductor device in parallel bits
11/23/1999	US5991902 Memory apparatus and data processor using the same
11/23/1999	US5991517 Flash EEprom system with cell by cell programming verification
11/23/1999	US5991232 Clock synchronous memory embedded semiconductor integrated circuit device
11/23/1999	US5991219 Semiconductor memory device provided with a sense amplifier having a trimming capability
11/23/1999	US5991218 Dynamic random access memory
11/23/1999	US5991215 Method for testing a memory chip in multiple passes
11/23/1999	US5991214 Circuit and method for varying a period of an internal control signal during a test mode
11/23/1999	US5991213 Short disturb test algorithm for built-in self-test
11/23/1999	US5991212 Semi-conductor integrated circuit device having an external memory and a test method therefor
11/23/1999	US5991211 Semiconductor memory device with redundancy control circuits
11/23/1999	US5991195 Flash EEPROM with erase verification and address scrambling architecture
11/23/1999	US5991189 Ferroelectric random access memory devices having short-lived cell detector available for life test for ferroelectric capacitor and method for testing ferroelectric memory cells
11/18/1999	DE19916077A1 Fuse layout structure for DRAM, SRAM
11/18/1999	DE19821459A1 Anordnung zur Redundanzauswertung bei einem Halbleiterspeicherchip Arrangement for redundancy analysis in a semiconductor memory chip
11/17/1999	EP0957430A1 Redundancy device in a semiconductor memory circuit
11/17/1999	CN1235691A Method and apparatus for correcting multilevel cell memory by using interleaving
11/17/1999	CN1235419A Semiconductor device for setting delay time
11/17/1999	CN1235353A Semiconductor memory device
11/17/1999	CN1235352A Synchronous semiconductor storage device
11/16/1999	US5987632 Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations
11/16/1999	US5987623 Terminal mapping apparatus
11/16/1999	US5986956 Repair control circuit
11/16/1999	US5986953 Input/output circuits and methods for testing integrated circuit memory devices
11/16/1999	US5986952 Redundancy concept for memory circuits having ROM memory cells
11/16/1999	US5986951 Address signal storage circuit of data repair controller
11/16/1999	US5986950 Use of redundant circuits to improve the reliability of an integrated circuit
11/16/1999	US5986944 Method and apparatus using a data read latch circuit in a semiconductor device
11/16/1999	US5986916 On-chip program voltage generator for antifuse repair
11/16/1999	US5986915 Semiconductor memory device capable of preventing malfunction due to disconnection of column select line or word select line
11/16/1999	US5986461 UV methods for screening open circuit defects in CMOS integrated circuits
11/16/1999	US5986357 Occupancy sensor and method of operating same
11/16/1999	US5986320 Semiconductor integrated circuit device
11/16/1999	US5985677 Method of repairing semiconductor memory, electron-beam memory repairing apparatus and redundancy memory circuit to which the method of repairing semiconductor memory is applicable
11/11/1999	WO1999057567A2 Method and apparatus for protecting sensitive data during automatic testing of hardware
11/11/1999	WO1999044113A9 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
11/11/1999	WO1999008116A3 A memory test system with a means for test sequence optimisation and a method of its operation
11/10/1999	EP0954866A1 Sdram clocking test mode
11/10/1999	EP0637036B1 Redundancy element check in IC memory without programming substitution of redundant elements
11/10/1999	EP0549193B1 Nonvolatile semiconductor memory device with redundancy
11/10/1999	CN1046369C Unlosable semiconductor memory device
11/09/1999	US5983378 Method tester and circuit for applying a pulse trigger to a unit to be triggered
11/09/1999	US5983375 Multi-bit test circuit and method thereof
11/09/1999	US5983374 Semiconductor test system and method, and medium for recording test program therefor
11/09/1999	US5983372 Failure counting method and device
11/09/1999	US5983358 Semiconductor memory having redundancy circuit
11/09/1999	US5983320 Method and apparatus for externally configuring and modifying the transaction request response characteristics of a semiconductor device coupled to a bus
11/09/1999	US5983312 Simultaneously writing to and erasing two commonly numbered sectors
11/09/1999	US5983009 Automatic generation of user definable memory BIST circuitry
11/09/1999	US5982691 Method and apparatus for determining the robustness of memory cells to induced soft errors using equivalent diodes
11/09/1999	US5982687 Method of detecting leakage within a memory cell capacitor
11/09/1999	US5982686 Memory circuit voltage regulator
11/09/1999	US5982685 Semiconductor device for test mode setup
11/09/1999	US5982684 Parallel access testing of a memory array
11/09/1999	US5982683 Enhanced method of testing semiconductor devices having nonvolatile elements
11/09/1999	US5982682 Self-test circuit for memory integrated circuits
11/09/1999	US5982681 Reconfigurable built-in self test circuit
11/09/1999	US5982680 Semiconductor memory
11/09/1999	US5982679 Memory circuit with dynamic redundancy
11/09/1999	US5982678 Semiconductor memory device with redundancy circuit
11/09/1999	US5982663 Nonvolatile semiconductor memory performing single bit and multi-bit operations
11/09/1999	US5982657 Circuit and method for biasing the charging capacitor of a semiconductor memory array
11/09/1999	US5982656 Method and apparatus for checking the resistance of programmable elements
11/04/1999	WO1999046778A3 High speed memory test system with intermediate storage buffer and method of testing
11/04/1999	WO1999027431A3 A memory redundancy allocation system and a method of redundancy allocation
11/04/1999	DE4341692C2 Reihenredundanzschaltkreis für eine Halbleiter-Speichervorrichtung Row redundancy circuit for a semiconductor memory device
11/04/1999	DE19819570A1 Anordnung zum Testen mehrerer Speicherchips auf einem Wafer Arrangement for testing multiple memory chips on a wafer
11/04/1999	DE19819205A1 Data retention system for persistent data
11/04/1999	DE19818853A1 Integrated logic circuit
11/03/1999	EP0954102A1 Exclusive or/nor circuits
11/03/1999	EP0953989A2 Static ram circuit for defect analysis
11/03/1999	EP0953988A2 Integrated circuit having memory built-in self test (BIST) with programmable characteristics and method of operation
11/03/1999	EP0953987A2 Synchronous semiconductor storage device
11/03/1999	EP0953986A2 Arrangement for testing multiple memory chips in a wafer
11/03/1999	EP0953983A2 Semiconductor memory device with clamping circuit for preventing malfunction
11/03/1999	EP0953912A2 Semiconductor memory device with redundancy
11/03/1999	EP0615252B1 Semiconductor memory with built-in parallel bit test mode
11/03/1999	CN1233841A Device for testing multiple memory chips of one crystal plate
11/03/1999	CN1233840A Circuit device and method for automatically checking and determining shor-tcircuit of word-line or position-line
11/02/1999	US5978958 Data transmission system, data recording and reproducing apparatus and recording medium each having data structure of error correcting code

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