| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 07/12/2000 | EP1018029A1 Programmable formatter circuit for integrated circuit tester |
| 07/11/2000 | US6088820 Static semiconductor memory device having test mode |
| 07/11/2000 | US6088819 Dynamic semiconductor memory device and method of testing the same |
| 07/11/2000 | US6088817 Fault tolerant queue system |
| 07/11/2000 | US6088281 Semiconductor memory device |
| 07/11/2000 | US6088274 Method and device for testing a semiconductor serial access memory device through a main memory |
| 07/11/2000 | US6087890 Redundancy fuse read circuit |
| 07/11/2000 | US6087190 Automatic test process with non-volatile result table store |
| 07/06/2000 | DE19963611A1 Memory test device in which information indicating that error location is present in memory device is written into compact memory |
| 07/05/2000 | EP1016089A1 Memory tester with data compression |
| 07/04/2000 | US6085346 Method and apparatus for built-in self test of integrated circuits |
| 07/04/2000 | US6085344 Data communication interface with memory access controller |
| 07/04/2000 | US6085341 Memory test mode for wordline resistive defects |
| 07/04/2000 | US6085334 Method and apparatus for testing an integrated memory device |
| 07/04/2000 | US6085284 Method of operating a memory device having a variable data output length and an identification register |
| 07/04/2000 | US6084818 Semiconductor memory device capable of efficient memory cell select operation with reduced element count |
| 07/04/2000 | US6084815 Semiconductor device |
| 07/04/2000 | US6084809 Main amplifier circuit and input-output bus for a dynamic random access memory |
| 07/04/2000 | US6084808 Circuits and methods for burn-in of integrated circuits using potential differences between adjacent main word lines |
| 07/04/2000 | US6084807 Memory device with global redundancy |
| 07/04/2000 | US6084806 Semiconductor memory device |
| 07/04/2000 | US6083982 Stimulating sodium excretion in the urine of a mammal comprising administering to the mammal a alkoxyalkyl or hydroxy alkyl substituted phenolic compound |
| 06/29/2000 | WO2000038067A1 Storage system comprising means managing a storage unit with anti-wear and anti-wear management of a storage unit |
| 06/29/2000 | WO2000038066A1 Integrated memory with redundancy |
| 06/29/2000 | WO2000038065A1 Ic memory having a redundancy |
| 06/29/2000 | WO2000037950A1 Lead frame structure for testing integrated circuits |
| 06/29/2000 | WO2000019443B1 Circuit for generating a reference voltage for reading out from a ferroelectric memory |
| 06/28/2000 | EP1014268A2 RAM configurable redundancy |
| 06/28/2000 | EP1014267A1 Method and apparatus for parallel redundancy in semiconductor memories |
| 06/28/2000 | EP1012849A1 Low cost, highly parallel memory tester |
| 06/28/2000 | EP1012848A1 Memory test system with defect compression |
| 06/28/2000 | EP0547844B1 Apparatus and method for controlling background processing in a disk array device |
| 06/28/2000 | CN1258078A Distributed block redundance of memory device |
| 06/27/2000 | US6081916 IC with test cells having separate data and test paths |
| 06/27/2000 | US6081911 Method and circuit architecture for testing a non-volatile memory device |
| 06/27/2000 | US6081910 Circuit for allowing a two-pass fuse blow to memory chips combining an array built-in self-test with redundancy capabilities |
| 06/27/2000 | US6081878 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
| 06/27/2000 | US6081467 Memory device having two or more memory arrays and a testpath operably connected to one of the memory arrays and not operably connected to another memory array, and a method of operating the testpath |
| 06/27/2000 | US6081466 Stress test mode entry at power up for low/zero power memories |
| 06/27/2000 | US6081465 Static RAM circuit for defect analysis |
| 06/27/2000 | US6081464 Circuit for SRAM test mode isolated bitline modulation |
| 06/27/2000 | US6081462 Adjustable delay circuit for setting the speed grade of a semiconductor device |
| 06/27/2000 | US6081454 Electrically erasable programmable read-only memory with threshold value controller for data programming |
| 06/22/2000 | WO2000036511A1 Method for storing and operating data units in a security module and associated security module |
| 06/21/2000 | DE19959779A1 Faulty cell identification information delivery device for semiconductor memory uses faulty cell specification memory, faulty cell block information memory and sub-block information memory |
| 06/21/2000 | CN1053757C Wafer burn-in test circuit of a semiconductor memory device |
| 06/20/2000 | US6079037 Method and apparatus for detecting intercell defects in a memory device |
| 06/20/2000 | US6078637 Address counter test mode for memory device |
| 06/20/2000 | US6078540 Selective power distribution circuit for an integrated circuit |
| 06/20/2000 | US6078538 Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts |
| 06/20/2000 | US6078536 Packet type integrated circuit memory devices having pins assigned direct test mode and associated methods |
| 06/20/2000 | US6078535 Redundancy arrangement for novel memory architecture |
| 06/20/2000 | US6078534 Semiconductor memory having redundancy circuit |
| 06/20/2000 | US6078533 Adjustable delay circuit for setting the speed grade of a semiconductor device |
| 06/20/2000 | US6078525 Non-volatile semiconductor memory device capable of pre-conditioning memory cells prior to a data erasure |
| 06/20/2000 | US6078520 Flash memory control method and information processing system therewith |
| 06/20/2000 | US6078519 Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell |
| 06/20/2000 | US6078253 Occupancy sensor and method of operating same |
| 06/20/2000 | US6078210 Internal voltage generating circuit |
| 06/20/2000 | US6077211 Circuits and methods for selectively coupling redundant elements into an integrated circuit |
| 06/15/2000 | DE19819570C2 Anordnung zum Testen mehrerer Speicherchips auf einem Wafer Arrangement for testing multiple memory chips on a wafer |
| 06/14/2000 | EP1008993A2 Writeable memory with self-test device and method therefor |
| 06/14/2000 | EP1008992A1 Semiconductor storage device |
| 06/14/2000 | EP1008937A1 Distributed block redundancy for memory devices |
| 06/14/2000 | EP1008936A2 Flash memory control method |
| 06/14/2000 | EP1008858A2 Circuit with logic circuit for temperature dependant semi-conductor element test and repair |
| 06/13/2000 | US6076176 Encoding of failing bit addresses to facilitate multi-bit failure detect using a wired-OR scheme |
| 06/13/2000 | US6075732 Semiconductor memory device with redundancy circuit |
| 06/13/2000 | US6075724 Method for sorting semiconductor devices having a plurality of non-volatile memory cells |
| 06/08/2000 | WO2000033190A1 Improved memory integrity for meters |
| 06/08/2000 | DE4242810C2 EEPROM mit einem Fehlerprüf- und Korrektur-Schaltkreis EEPROM with an error check and correction circuit |
| 06/08/2000 | DE19956550A1 Large scale integrated circuit has reference potential control circuit for controlling reference potential within each memory device of large scale integrated circuit |
| 06/08/2000 | DE19725581C2 Verfahren zur Funktionsüberprüfung von Speicherzellen eines integrierten Speichers Method for functional testing of memory cells of an integrated memory |
| 06/07/2000 | EP1006444A2 Method and apparatus for testing random access memory device |
| 06/07/2000 | CN1256005A Encoding method and memory device |
| 06/06/2000 | US6073267 Semiconductor integrated circuit with error detecting circuit |
| 06/06/2000 | US6073258 Method and device for performing two dimensional redundancy calculations on embedded memories avoiding fail data collection |
| 06/06/2000 | US6072737 Method and apparatus for testing embedded DRAM |
| 06/06/2000 | US6072736 Semiconductor memory device |
| 06/06/2000 | US6072729 Data-output driver circuit and method |
| 05/31/2000 | EP1004956A2 Integrated I/O circuit using a high performance bus interface |
| 05/31/2000 | DE19940871A1 Diagnostic device for random access memory used in microcomputer of motor vehicle engine, performs failure prevention process based on diagnostic result stored in predefined register during failure |
| 05/30/2000 | US6070262 Reconfigurable I/O DRAM |
| 05/30/2000 | US6070257 Integration type input circuit and method of testing it |
| 05/30/2000 | US6070256 Method and apparatus for self-testing multi-port RAMs |
| 05/30/2000 | US6070232 Cache controller fault tolerant computer and data transfer system setting recovery points |
| 05/30/2000 | US6070222 Synchronous memory device having identification register |
| 05/30/2000 | US6069829 Internal clock multiplication for test time reduction |
| 05/30/2000 | US6069817 Memory device evaluation methods using test capacitor patterns |
| 05/25/2000 | WO2000019443A3 Circuit for generating a reference voltage for reading out from a ferroelectric memory |
| 05/25/2000 | DE19852430A1 Circuit arrangement with temperature dependent semiconductor test and repair logic |
| 05/24/2000 | EP0674320B1 Memory device with programmable self-refreshing and testing methods therefore |
| 05/24/2000 | CN1254186A Electric fuse with close space length and its production method in semiconductor |
| 05/23/2000 | US6067649 Method and apparatus for a low power self test of a memory subsystem |
| 05/23/2000 | US6067648 Programmable pulse generator |
| 05/23/2000 | US6067598 Memory system having programmable flow control register |
| 05/23/2000 | US6067592 System having a synchronous memory device |
| 05/23/2000 | US6067269 Semiconductor memory device capable of operating at a low power supply voltage |
| 05/23/2000 | US6067268 Redundancy fuse box and method for arranging the same |
| 05/23/2000 | US6067263 Dynamic random access memory circuit having a testing system and method to determine the sensitivity of a sense amplifier |