| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 08/22/2000 | US6108804 Method and apparatus for testing adjustment of a circuit parameter |
| 08/22/2000 | US6108803 Memory cell circuit for executing specific tests on memory cells that have been designated by address data |
| 08/22/2000 | US6108802 Testing method and apparatus for first-in first-out memories |
| 08/22/2000 | US6108797 Method and system for loading microprograms in partially defective memory |
| 08/22/2000 | US6108762 Address processor and method therefor |
| 08/22/2000 | US6108730 Memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket |
| 08/22/2000 | US6108261 Repair circuit for redundancy circuit with anti-fuse |
| 08/22/2000 | US6108260 Antifuse detect circuit |
| 08/22/2000 | US6108253 Failure analysis system, fatal failure extraction method and recording medium |
| 08/22/2000 | US6108252 Integrated circuit memory devices having self-test circuits therein and method of testing same |
| 08/22/2000 | US6108251 Method and apparatus for remapping memory addresses for redundancy |
| 08/22/2000 | US6108250 Fast redundancy scheme for high density, high speed memories |
| 08/22/2000 | US6108248 Column address strobe signal generator for synchronous dynamic random access memory |
| 08/22/2000 | US6108246 Semiconductor memory device |
| 08/22/2000 | US6107817 UV methods for screening open circuit defects in CMOS integrated circuits |
| 08/22/2000 | US6107815 Test circuit and testing method for function testing of electronic circuits |
| 08/16/2000 | EP1028367A1 Device and method for improving the write performances of a computer data storage peripheral |
| 08/16/2000 | EP1027707A1 Method for testing the bus terminals of writable-readable integrated electronic integrated circuits, especially of memory chips |
| 08/16/2000 | EP0912979B1 Semiconductor memory tester with redundancy analysis |
| 08/16/2000 | EP0782747B1 Memory with stress circuitry for detecting defects |
| 08/16/2000 | EP0578935B1 Row redundancy circuit of a semiconductor memory device |
| 08/15/2000 | US6105161 Error data correction circuit |
| 08/15/2000 | US6105152 Devices and methods for testing cell margin of memory devices |
| 08/15/2000 | US6104669 Method and apparatus for generating memory addresses for testing memory devices |
| 08/15/2000 | US6104651 Testing parameters of an electronic device |
| 08/15/2000 | US6104650 Sacrifice read test mode |
| 08/15/2000 | US6104649 Semiconductor memory device |
| 08/15/2000 | US6104648 Semiconductor memory device having a large band width and allowing efficient execution of redundant repair |
| 08/15/2000 | US6104647 Semiconductor device having redundancy circuit |
| 08/15/2000 | US6104646 Semiconductor memory device having redundancy circuit with high rescue efficiency |
| 08/15/2000 | US6104645 High speed global row redundancy system |
| 08/15/2000 | US6104634 Electrical programmable non-volatile memory integrated circuit with option configuration register |
| 08/10/2000 | WO2000046810A1 Method for functionally testing memory cells of an integrated semiconductor memory |
| 08/10/2000 | DE19843435C2 Burn-In-Testvorrichtung Burn-in test device |
| 08/09/2000 | EP1026697A2 Method for stress testing a memory cell oxide of a dram |
| 08/09/2000 | EP1026696A2 Test method and test circuit for electronic device |
| 08/09/2000 | EP1025564A1 Programmable logic device memory cell circuit |
| 08/08/2000 | US6101623 Current reduction circuit for testing purpose |
| 08/08/2000 | US6101620 Testable interleaved dual-DRAM architecture for a video memory controller with split internal/external memory |
| 08/08/2000 | US6101618 Method and device for acquiring redundancy information from a packaged memory chip |
| 08/08/2000 | US6101617 Computer failure recovery and alert system |
| 08/08/2000 | US6101587 Data protection circuit for semiconductor memory device |
| 08/08/2000 | US6101578 Method and apparatus for providing test mode access to an instruction cache and microcode ROM |
| 08/08/2000 | US6101152 Method of operating a synchronous memory device |
| 08/08/2000 | US6101150 Method and apparatus for using supply voltage for testing in semiconductor memory devices |
| 08/08/2000 | US6101148 Dynamic random access memory |
| 08/08/2000 | US6101139 Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
| 08/08/2000 | US6101138 Area efficient global row redundancy scheme for DRAM |
| 08/08/2000 | US6100748 Redundant circuit for semiconductor device having a controllable high voltage generator |
| 08/08/2000 | US6100739 Self-timed synchronous pulse generator with test mode |
| 08/02/2000 | EP1024500A2 Test circuit for boost circuit output node potential measurement of a semiconductor ic device |
| 08/02/2000 | EP1024431A2 Antifuse circuitry for post-package dram repair |
| 08/02/2000 | EP0572027B1 Semiconductor memory device with spare columns |
| 08/02/2000 | EP0454051B1 Program element for use in redundancy technique for semiconductor memory device, and method of fabricating a semiconductor memory device having the same |
| 08/01/2000 | US6098077 Data management apparatus, data management method, and recording medium |
| 08/01/2000 | US6097665 Dynamic semiconductor memory device having excellent charge retention characteristics |
| 08/01/2000 | US6097647 Efficient method for obtaining usable parts from a partially good memory integrated circuit |
| 08/01/2000 | US6097646 Method for the testing of a dynamic memory |
| 08/01/2000 | US6097645 High speed column redundancy scheme |
| 08/01/2000 | US6097644 Redundant row topology circuit, and memory device and test system using same |
| 08/01/2000 | US6097643 Semiconductor storage apparatus and method of manufacturing of the same |
| 08/01/2000 | US6097211 Configuration memory integrated circuit |
| 08/01/2000 | US6097206 Memory tester and method of switching the tester to RAM test mode and ROM test mode |
| 07/27/2000 | WO2000044001A1 Nonvolatile semiconductor storage device |
| 07/27/2000 | DE19901206A1 Verfahren zur Reparatur von defekten Speicherzellen eines integrierten Halbleiterspeichers A method for repairing defective memory cells of an integrated semiconductor memory, |
| 07/26/2000 | EP1022642A1 Integrated circuit I/O using a high performance bus interface |
| 07/26/2000 | EP1022641A1 Integrated circuit i/o using a high performance bus interface |
| 07/26/2000 | EP0792507B1 Circuits, systems, and methods for accounting for defective cells in a memory device |
| 07/25/2000 | US6094736 Semiconductor integrated circuit device |
| 07/25/2000 | US6094734 Test arrangement for memory devices using a dynamic row for creating test data |
| 07/25/2000 | US6094733 Method for testing semiconductor memory devices, and apparatus and system for testing semiconductor memory devices |
| 07/25/2000 | US6094389 Semiconductor memory apparatus having refresh test circuit |
| 07/25/2000 | US6094388 Methods of identifying defects in an array of memory cells and related integrated circuitry |
| 07/25/2000 | US6094387 Roll call tester |
| 07/25/2000 | US6094386 Semiconductor memory device of redundant circuit system |
| 07/25/2000 | US6094384 Column redundancy circuit |
| 07/25/2000 | US6094382 Integrated circuit memory devices with improved layout of fuse boxes and buses |
| 07/25/2000 | US6094381 Semiconductor memory device with redundancy circuit |
| 07/25/2000 | US6094377 Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell |
| 07/25/2000 | US6094373 Nonvolatile semiconductor memory device |
| 07/19/2000 | EP1020795A1 Method for repairing faulty cells in an integrated semiconductor memory |
| 07/19/2000 | EP1019910A1 Selective power distribution circuit for an integrated circuit |
| 07/19/2000 | EP1019824A2 Method for generating an error identification signal in the data inventory of a memory, and device designed for that purpose |
| 07/19/2000 | EP1019821A4 Method and apparatus for correcting a multilevel cell memory by using interleaving |
| 07/19/2000 | EP1019821A1 Method and apparatus for correcting a multilevel cell memory by using interleaving |
| 07/19/2000 | EP0764330A4 Eeprom array with flash-like core |
| 07/18/2000 | US6092232 Disk data reproducing apparatus and disk data reproducing method |
| 07/18/2000 | US6092227 Test circuit |
| 07/18/2000 | US6092223 Redundancy circuit for semiconductor integrated circuit |
| 07/18/2000 | US6092221 Method for calculating remaining life of semiconductor disk device |
| 07/18/2000 | US6092164 Microcomputer having division of timing signals to initialize flash memory |
| 07/18/2000 | US6091655 Semiconductor memory |
| 07/18/2000 | US6091652 Testing semiconductor devices for data retention |
| 07/18/2000 | US6091651 Semiconductor memory device with improved test efficiency |
| 07/18/2000 | US6091649 Integrated circuit memory devices having built-in self test based redundancy and methods of operation thereof |
| 07/18/2000 | US6091290 Semiconductor integrated circuit |
| 07/18/2000 | US6091258 Redundancy circuitry for logic circuits |
| 07/13/2000 | WO2000041240A1 Vertically integrated circuit system |
| 07/13/2000 | WO2000040986A1 Pattern generator for a packet-based memory tester |
| 07/12/2000 | EP1018120A1 Digital storage and operating method for the same |