Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
10/2000
10/03/2000US6127838 IDDQ testable programmable logic arrays
10/03/2000US6127834 Apparatus for testing an integrated circuit in an oven during burn-in
09/2000
09/27/2000EP1039478A1 Integrated circiut memory having a fuse detect circuit and method therefor
09/27/2000EP1039388A2 Block erasable semiconductor memory device with defective block replacement
09/27/2000EP1039385A1 Semiconductor read-only memory device having means for replacing defective memory cells
09/27/2000EP1038223A1 Monitoring system for a digital trimming cell
09/27/2000CN1267889A Parallel redundant method and apparatus for semi-conductor storage
09/27/2000CN1267888A Semi-conductor storage with block unit to erase
09/26/2000US6125460 Method for testing semiconductor device having embedded nonvolatile memory
09/26/2000US6125435 Alignment of cluster address to block addresses within a semiconductor non-volatile mass storage memory
09/26/2000US6125424 Method of writing, erasing, and controlling memory and memory device having erasing and moving components
09/26/2000US6125069 Semiconductor memory device with redundancy circuit having a reference resistance
09/26/2000US6125068 Memory access control
09/26/2000US6125067 Device and method for repairing a semiconductor memory
09/26/2000US6125066 Circuit configuration and method for automatic recognition and elimination of word line/bit line short circuits
09/26/2000US6125063 Integrated circuit with memory comprising an internal circuit for the generation of a programming high voltage
09/26/2000US6125058 System for optimizing the equalization pulse of a read sense amplifier for a simultaneous operation flash memory device
09/26/2000US6125054 Rom data read protect circuit
09/21/2000WO2000055863A1 Device and method for carrying out the built-in self-test of an electronic circuit
09/20/2000EP1036364A1 Alignment of cluster address to block addresses within a semiconductor non-volatile mass storage memory
09/20/2000EP0496506B1 Fault tolerant computer system incorporating processing units which have at least three processors
09/19/2000USRE36875 Semiconductor memory device capable of performing test mode operation and method of operating such semiconductor device
09/19/2000US6122762 Memory interface device and method for supporting debugging
09/19/2000US6122760 Burn in technique for chips containing different types of IC circuitry
09/19/2000US6122574 Method for detecting abnormality of control unit and control unit employing same
09/19/2000US6122213 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
09/19/2000US6122208 Circuit and method for column redundancy for high bandwidth memories
09/19/2000US6122207 Semiconductor memory device and method for relieving defective memory cells
09/19/2000US6122206 Semiconductor memory device having means for outputting redundancy replacement selection signal for each bank
09/19/2000US6122194 Semiconductor memory device with a column redundancy occupying a less chip area
09/19/2000US6122190 Semiconductor memory device capable of high speed plural parallel test
09/19/2000US6121820 Semiconductor device having fuse and method for checking whether the fuse is fused
09/19/2000US6121806 Circuit for adjusting a voltage level in a semiconductor device
09/14/2000DE4243592C2 Paralleltestschaltung für einen Halbleiter-Speicherchip Parallel test circuitry for a semiconductor memory chip
09/13/2000CN1266285A Refractory fuse circuit for packaged DRAM repair
09/12/2000US6119257 Semiconductor device testing apparatus capable of high speed test operation
09/12/2000US6119252 Integrated circuit test mode with externally forced reference voltage
09/12/2000US6119251 Self-test of a memory device
09/12/2000US6119249 Memory devices operable in both a normal and a test mode and methods for testing same
09/12/2000US6119049 Memory module assembly using partially defective chips
09/12/2000US6118728 Circuit and method for memory device with defect current isolation
09/12/2000US6118727 Semiconductor memory with interdigitated array having bit line pairs accessible from either of two sides of the array
09/12/2000US6118713 Device and method for stress testing a semiconduction memory
09/12/2000US6118712 Redundancy fuse boxes and redundancy repair structures for semiconductor devices
09/12/2000US6118711 Apparatus for testing redundant elements in a packaged semiconductor memory device
09/12/2000US6118710 Semiconductor memory device including disturb refresh test circuit
09/12/2000US6118709 Externally controlled power on reset device for non-volatile memory in integrated circuit form
09/12/2000US6118701 Method and apparatus capable of trimming a nonvolatile semiconductor storage device without any superfluous pads or terminals
09/12/2000US6118693 Electrically erasable non-volatile memory cell with integrated SRAM cell to reduce testing time
09/12/2000US6118296 Semiconductor integrated logic circuit
09/12/2000US6118294 Integrated circuit testing device
09/12/2000US6115925 Probepin-adjusting jig
09/08/2000WO2000052703A1 Parallel testing of integrated circuit devices using cross-dut and within-dut comparisons
09/08/2000WO2000052578A1 Microcomputer with redundant memory areas
09/08/2000WO2000052488A1 Distributed interface for parallel testing of multiple devices using a single tester channel
09/07/2000DE19908430A1 Mikrocomputer Microcomputer
09/06/2000EP1033029A2 Affine transformation means and method of affine transformation
09/06/2000EP1032870A2 A memory redundancy allocation system and a method of redundancy allocation
09/05/2000US6115837 Dual-column syndrome generation for DVD error correction using an embedded DRAM
09/05/2000US6115834 Method for quickly identifying floating cells by a bit-line coupling pattern (BLCP)
09/05/2000US6115833 Semiconductor memory testing apparatus
09/05/2000US6115828 Method of replacing failed memory cells in semiconductor memory device
09/05/2000US6115789 Method and system for determining which memory locations have been accessed in a self timed cache architecture
09/05/2000US6115785 Direct logical block addressing flash memory mass storage architecture
09/05/2000US6115783 Integrated circuit
09/05/2000US6115312 Programmable logic device memory cell circuit
09/05/2000US6115306 Method and apparatus for multiple row activation in memory devices
09/05/2000US6115305 Method and apparatus for testing a video display chip
09/05/2000US6115304 Semiconductor memory device and method of burn-in testing
09/05/2000US6115303 Method and apparatus for testing memory devices
09/05/2000US6115302 Disabling a decoder for a defective element in an integrated circuit device having redundant elements
09/05/2000US6115301 Semiconductor memory device having defect relieving system using data line shift method
09/05/2000US6115300 Column redundancy based on column slices
09/05/2000US6115299 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
09/05/2000US6115293 Non-volatile semiconductor memory device
09/05/2000US6115286 Data memory
09/05/2000US6115283 Semiconductor device with programming capacitance element
09/05/2000US6112797 Apparatus for fabricating a light control window covering
08/2000
08/31/2000WO2000050996A1 Method and apparatus for memory redundancy with no critical delay-path
08/30/2000EP1032040A2 Metal wire fuse structure with cavity
08/30/2000EP1031995A1 Built-in self-test circuit for memory
08/30/2000EP1031994A1 Built-in self-test circuit for memory
08/30/2000EP1031992A2 Flash EEPROM system
08/29/2000USRE36842 Semiconductor memory device for maintaining level of signal line
08/29/2000US6112322 Circuit and method for stress testing EEPROMS
08/29/2000US6112321 Nonvolatile semiconductor storage device
08/29/2000US6112314 Apparatus and method for detecting over-programming condition in multistate memory device
08/29/2000US6111807 Synchronous semiconductor memory device allowing easy and fast text
08/29/2000US6111801 Technique for testing wordline and related circuitry of a memory array
08/29/2000US6111800 Parallel test for asynchronous memory
08/29/2000US6111798 Fuse repair circuit for semiconductor memory circuit
08/29/2000US6111794 Memory interface circuit including bypass data forwarding with essentially no delay
08/29/2000US6111786 Semiconductor electrically erasable and programmable read only memory device for concurrently writing data bits into memory cells selected from sectors and method for controlling the multi-write operation
08/29/2000US6111785 Nonvolatile semiconductor memory device capable of decreasing layout area for writing defective address
08/24/2000DE19680641C2 Fehlerspeicher-Analysiervorrichtung in einem Halbleiterspeichertestsystem Error analyzer memory in a semiconductor memory test system
08/23/2000EP1030314A1 Device and method for testing a non-volatile reprogrammable memory
08/23/2000EP1030313A2 Semiconductor device having test mode entry circuit
08/23/2000EP1029278A1 Moving sequential sectors within a block of information in a flash memory mass storage architecture
08/23/2000EP0642685B1 Improved solid state storage device
08/23/2000CN1264127A Semiconductor memory device with redundancy memory circuit
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