| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 03/02/2000 | CA2341014A1 A system and method for defining transforms of memory device addresses |
| 03/01/2000 | EP0982738A1 A nonvolatile memory |
| 02/29/2000 | US6032281 Test pattern generator for memories having a block write function |
| 02/29/2000 | US6032275 Test pattern generator |
| 02/29/2000 | US6032274 Method and apparatus for compressed data testing of more than one memory array |
| 02/29/2000 | US6032264 Apparatus and method implementing repairs on a memory device |
| 02/29/2000 | US6032221 Flash memory embedded microcomputer |
| 02/29/2000 | US6032215 Synchronous memory device utilizing two external clocks |
| 02/29/2000 | US6032214 Method of operating a synchronous memory device having a variable data output length |
| 02/29/2000 | US6031786 Operation control circuits and methods for integrated circuit memory devices |
| 02/29/2000 | US6031777 Fast on-chip current measurement circuit and method for use with memory array circuits |
| 02/29/2000 | US6031773 Method for stress testing the memory cell oxide of a DRAM capacitor |
| 02/29/2000 | US6031772 Semiconductor memory device having floating gate transistors |
| 02/29/2000 | US6031771 Memory redundancy circuit using single polysilicon floating gate transistors as redundancy elements |
| 02/29/2000 | US6031763 Evaluation of memory cell characteristics |
| 02/29/2000 | US6031758 Semiconductor memory device having faulty cells |
| 02/29/2000 | US6031411 Low power substrate bias circuit |
| 02/29/2000 | US6031391 Configuration memory integrated circuit |
| 02/24/2000 | WO2000010088A1 A system, method, and program for detecting and assuring dram arrays |
| 02/24/2000 | WO2000010086A1 Integrated storage with inter-block redundancy |
| 02/24/2000 | DE19933792A1 Memory test unit for applying preset test pattern signal to semiconductor memory; has sections to produce two time control pulses and two nonreturn to zero waveforms |
| 02/23/2000 | EP0981134A2 Signal processing apparatus having non-volatile memory and programming method of the non-volatile memory |
| 02/23/2000 | EP0980551A1 Moving sectors within a block in a flash memory |
| 02/22/2000 | US6029260 Memory analyzing apparatus |
| 02/22/2000 | US6029254 Method for synchronizing reserved areas in a redundant storage array |
| 02/22/2000 | US6028799 Memory circuit voltage regulator |
| 02/22/2000 | US6028798 Low voltage test mode operation enable scheme with hardware safeguard |
| 02/17/2000 | WO2000008563A1 Redundant, asymmetrically parallel disk cache for a data storage system |
| 02/17/2000 | DE19937320A1 Integrated circuit structural element; has externally accessible signal line at capsule containing integrated circuit chip connected to signal line with operating mode selective signal production circuit for operating mode control signal |
| 02/17/2000 | DE19937101A1 Semiconductor memory device error correction method, simultaneously corrects data from two groups of stored data bits |
| 02/17/2000 | DE19836578A1 Integrated memory device with inter-array redundancy |
| 02/16/2000 | EP0891623B1 Circuit arrangement with a test circuit |
| 02/15/2000 | US6026505 Method and apparatus for real time two dimensional redundancy allocation |
| 02/15/2000 | US6026052 Programmable semiconductor memory device |
| 02/15/2000 | US6026040 Method of altering the margin affecting a memory cell |
| 02/15/2000 | US6026039 Parallel test circuit for semiconductor memory |
| 02/15/2000 | US6026038 Wafer burn-in test circuit and method for testing a semiconductor memory |
| 02/15/2000 | US6026037 Repair circuit of memory cell array |
| 02/15/2000 | US6026036 Synchronous semiconductor memory device having set up time of external address signal reduced |
| 02/15/2000 | US6025733 Semiconductor memory device |
| 02/10/2000 | DE19861088A1 Repairing integrated circuits by replacing subassemblies with substitutes |
| 02/10/2000 | DE19835258A1 Integrated circuit with built-in self-test device |
| 02/09/2000 | EP0978846A2 Timing of wordline activation for DC burn-in of a dram with the self-refresh |
| 02/09/2000 | EP0978125A1 System for optimizing memory repair time using test data |
| 02/09/2000 | EP0978124A1 A method for testing integrated memory using an integrated dma controller |
| 02/08/2000 | US6023777 Testing method for devices with status flags |
| 02/08/2000 | US6023770 Semiconductor device |
| 02/08/2000 | US6023746 Dual associative-cache directories allowing simultaneous read operation using two buses with multiplexors, address tags, memory block control signals, single clock cycle operation and error correction |
| 02/08/2000 | US6023434 Method and apparatus for multiple row activation in memory devices |
| 02/08/2000 | US6023433 Semiconductor memory device with a redundant decoder having a small scale in circuitry |
| 02/08/2000 | US6023432 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array |
| 02/08/2000 | US6023431 Low current redundancy anti-fuse method and apparatus |
| 02/03/2000 | WO2000005723A2 Integrated circuit comprising a self-test device for executing a self-test of the integrated circuit |
| 02/02/2000 | EP0977120A1 Error correction in a ROM by means of redundancy |
| 02/02/2000 | EP0714546B1 Erase and program verification circuit for non-volatile memory |
| 02/01/2000 | US6021515 Pattern generator for semiconductor test system |
| 02/01/2000 | US6021512 Data processing system having memory sub-array redundancy and method therefor |
| 02/01/2000 | US6021075 Semiconductor memory circuit having shift redundancy circuits |
| 02/01/2000 | US6021067 Circuit of sensing a fuse cell in a flash memory |
| 02/01/2000 | US6019502 Test circuits and methods for built-in testing integrated devices |
| 02/01/2000 | US6019501 Address generating device for memory tester |
| 01/27/2000 | WO1999057567A3 Method and apparatus for protecting sensitive data during automatic testing of hardware |
| 01/27/2000 | DE19933894A1 Semiconductor memory and the process used to handle fault conditions uses redundance selection lines coupled to the address decoder and a shift redundance circuit |
| 01/26/2000 | EP0974905A2 An integrated circuit memory device with redundancy |
| 01/26/2000 | EP0974847A2 Arrangement and method to store the test results of a BIST-circuit |
| 01/26/2000 | EP0617363B1 Defective cell substitution in EEprom array |
| 01/25/2000 | US6018815 Adaptable scan chains for debugging and manufacturing test purposes |
| 01/25/2000 | US6018812 Reliable wafer-scale integrated computing systems |
| 01/25/2000 | US6018811 Layout for semiconductor memory device wherein intercoupling lines are shared by two sets of fuse banks and two sets of redundant elements not simultaneously active |
| 01/25/2000 | US6018790 Data access from the one of multiple redundant out-of-sync disks with the calculated shortest access time |
| 01/25/2000 | US6018485 Semiconductor memory device with cascaded burn-in test capability |
| 01/25/2000 | US6018484 Method and apparatus for testing random access memory devices |
| 01/25/2000 | US6018483 Distributed block redundancy for memory devices |
| 01/25/2000 | US6018482 High efficiency redundancy scheme for semiconductor memory device |
| 01/25/2000 | US6018481 Dynamic semiconductor memory device |
| 01/25/2000 | US6018253 Register with current-steering input network |
| 01/20/2000 | WO2000003258A1 Integrated circuit with improved synchronism for an external clock signal at a data output |
| 01/20/2000 | DE19831572A1 Anordnung und Verfahren zum Speichern der mit einer BIST-Schaltung erhaltenen Testergebnisse Apparatus and method for storing the obtained with a BIST circuit test results |
| 01/19/2000 | CN1242088A Method and apparatus for correcting a multilevel cell memory by using error locating codes |
| 01/19/2000 | CN1241787A ROM data verification circuit |
| 01/18/2000 | US6016561 Output data compression scheme for use in testing IC memories |
| 01/18/2000 | US6016560 Semiconductor memory, memory device, and memory card |
| 01/18/2000 | US6016281 Memory with word line voltage control |
| 01/18/2000 | US6016278 Failure analysis method and device |
| 01/13/2000 | WO2000002126A1 Method and apparatus for performing erase operations transparent to a solid state storage system |
| 01/13/2000 | DE19928981A1 Semiconductor memory testing device, e.g. for quality control testing |
| 01/13/2000 | DE19830571A1 Integrierte Schaltung Integrated circuit |
| 01/12/2000 | EP0971483A2 Deinterleaving device |
| 01/12/2000 | EP0971362A1 Data entegrity checking apparatus |
| 01/12/2000 | EP0768538B1 Method and tester for applying a pulse trigger to a unit to be triggered |
| 01/12/2000 | CN1241000A Fuse circuit and redundant decoder |
| 01/11/2000 | US6014766 Digital signal reproduction apparatus |
| 01/11/2000 | US6014762 Method and apparatus for scan test of SRAM for microprocessor without full scan capability |
| 01/11/2000 | US6014759 Method and apparatus for transferring test data from a memory array |
| 01/11/2000 | US6014755 Method of managing defects in flash disk memories |
| 01/11/2000 | US6014341 Synchronous-type semiconductor storage |
| 01/11/2000 | US6014336 Test enable control for built-in self-test |
| 01/11/2000 | US6014335 Semiconductor memory device |
| 01/11/2000 | US6014329 Flash-erasable semiconductor memory device having an improved reliability |
| 01/06/2000 | WO2000000837A1 A skew calibration means and a method of skew calibration |