| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
|---|
| 03/21/2001 | EP0588425B1 Electronic drive circuits for active matrix devices, and a method of self-testing and programming such circuits |
| 03/21/2001 | EP0570597B1 Flash memory improved in erasing characteristic, and circuit therefor |
| 03/21/2001 | CN1288262A Method and device for replacing non-working metallic wire for dynamic random access memory |
| 03/21/2001 | CN1288237A Integrated storage unit having at least two slice frayments |
| 03/21/2001 | CN1288236A Integrated storage unit having storage cells and reference unit |
| 03/20/2001 | US6205564 Optimized built-in self-test method and apparatus for random access memories |
| 03/20/2001 | US6205515 Column redundancy circuitry with reduced time delay |
| 03/20/2001 | US6205067 Semiconductor memory device having burn-in mode operation stably accelerated |
| 03/20/2001 | US6205065 Semiconductor memory device having redundancy memory circuit |
| 03/20/2001 | US6205064 Semiconductor memory device having program circuit |
| 03/20/2001 | US6205063 Apparatus and method for efficiently correcting defects in memory circuits |
| 03/20/2001 | US6205050 Programmed circuit in a semiconductor device |
| 03/20/2001 | US6204679 Low cost memory tester with high throughput |
| 03/20/2001 | US6204516 Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors |
| 03/15/2001 | DE19947118C1 Verfahren und Schaltungsanordnung zum Bewerten des Informationsgehalts einer Speicherzelle Method and circuit for evaluating the information content of a memory cell |
| 03/15/2001 | DE19933980A1 Integrated semiconductor memory with redundant memory cell devices and method for operating it causes memory cells to combine in standard devices with single addresses and a redundant device to replace one of the standard devices. |
| 03/15/2001 | DE10043397A1 Flash memory device with programming state diagnosis circuit, includes column drive circuit and programming state diagnosis circuit for verifying data bits from column drive are associated with programming state |
| 03/14/2001 | EP1083575A1 Non volatile memory with detection of short circuits between word lines |
| 03/14/2001 | EP1083573A1 Variable width content addressable memory device for searching variable with data |
| 03/14/2001 | EP1083572A1 Three port content addressable memory device and methods for implementing the same |
| 03/14/2001 | EP0634751B1 Method and apparatus for parallel testing of memory |
| 03/14/2001 | CN1287362A Non-volatile semiconductor memory |
| 03/13/2001 | US6202180 Semiconductor memory capable of relieving a defective memory cell by exchanging addresses |
| 03/13/2001 | US6202179 Method and apparatus for testing cells in a memory device with compressed data and for replacing defective cells |
| 03/13/2001 | US6202138 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
| 03/13/2001 | US6201762 EPROM circuit with error correction |
| 03/13/2001 | US6201754 Semiconductor memory device having function of supplying stable power supply voltage |
| 03/13/2001 | US6201752 Timing circuit for high voltage testing |
| 03/13/2001 | US6201748 Semiconductor memory device having test mode |
| 03/13/2001 | US6201747 Method and apparatus for measuring subthreshold current in a memory array |
| 03/13/2001 | US6201746 Test method for high speed memory devices in which limit conditions for the clock are defined |
| 03/13/2001 | US6201745 Semiconductor memory device with redundant row substitution architecture and a method of driving a row thereof |
| 03/13/2001 | US6201744 Semiconductor memory circuit and redundancy control method |
| 03/13/2001 | US6201733 Semiconductor integrated circuit device, memory module and storage device |
| 03/13/2001 | US6201432 Integrated circuit devices using fuse elements to generate an output signal that is independent of cut fuse remnants |
| 03/10/2001 | CA2318019A1 Content addressable memory having read/write capabilities that do not interrupt continuous search cycles |
| 03/10/2001 | CA2317902A1 Three port content addressable memory device and methods for implementing the same |
| 03/10/2001 | CA2317387A1 Variable width content addressable memory device for searching variable width data |
| 03/08/2001 | WO2001016956A1 Method and apparatus for supplying regulated power to memory device components |
| 03/08/2001 | WO2001016955A1 Circuit and method for a multiplexed redundancy scheme in a memory device |
| 03/08/2001 | WO2001016612A1 Variable length pattern generator for chip tester system |
| 03/08/2001 | DE19913570C2 Betriebsverfahren für einen integrierten Speicher und integrierter Speicher A method of operating an integrated memory and built-in memory |
| 03/08/2001 | DE10040454A1 Testing embedded analogue or mixed signal components of integrated system chip involves installing assembler program to generate test pattern for analogue component, evaluating response |
| 03/07/2001 | EP1081715A1 Logic-merged memory |
| 03/07/2001 | EP1081595A2 Semiconductor apparatus |
| 03/07/2001 | EP1080471A2 High speed memory test system with intermediate storage buffer and method of testing |
| 03/07/2001 | EP0686978B1 A method for in-factory testing of flash EEPROM devices |
| 03/06/2001 | US6199185 Test method for high speed semiconductor devices using a clock modulation technique |
| 03/06/2001 | US6199182 Probeless testing of pad buffers on wafer |
| 03/06/2001 | US6199177 Device and method for repairing a semiconductor memory |
| 03/06/2001 | US6199139 Refresh period control apparatus and method, and computer |
| 03/06/2001 | US6199025 Semiconductor device having selectable device type and methods of testing device operation |
| 03/06/2001 | US6198699 Semiconductor testing apparatus |
| 03/06/2001 | US6198676 Test device |
| 03/06/2001 | US6198675 RAM configurable redundancy |
| 03/06/2001 | US6198669 Semiconductor integrated circuit |
| 03/06/2001 | US6198667 Plural memory banks device that can simultaneously read from or write to all of the memory banks during testing |
| 03/06/2001 | US6198663 Non-volatile semiconductor memory IC |
| 03/06/2001 | US6198659 Defective address data storage circuit for nonvolatile semiconductor memory device having redundant function and method of writing defective address data |
| 03/06/2001 | US6198274 IC testing apparatus |
| 03/01/2001 | WO2001015174A1 A memory module test system with reduced driver output impedance |
| 03/01/2001 | WO2001015172A2 Flash memory with externally triggered detection and repair of leaky cells |
| 03/01/2001 | WO2001014972A1 Apparatus for monitoring lsi memory device |
| 03/01/2001 | DE19935497A1 Verfahren und Schaltungsanordnung zum Korrigieren von Speicherfehlern Method and circuit for correcting memory errors |
| 03/01/2001 | DE10035705A1 Defective relief analysis procedure of memory, involves detecting line or row address of defective cell in searched memory area, and specifying and storing address of defective cell |
| 03/01/2001 | DE10035690A1 Semiconductor memory device has input/output mode set by shifting levels of signals received at contacts of mode setting circuit |
| 02/28/2001 | EP0860017A4 Loosely coupled mass storage computer cluster |
| 02/28/2001 | EP0620556B1 Semiconductor memory device having register for holding test resultant signal |
| 02/28/2001 | CN1062668C FIFO buffer system having an error detection and correction device |
| 02/27/2001 | US6195771 Semiconductor device having semiconductor memory circuit to be tested, method of testing semiconductor memory circuit and read circuit for semiconductor memory circuit |
| 02/27/2001 | US6195299 Semiconductor memory device having an address exchanging circuit |
| 02/22/2001 | DE10034702A1 Analysing and repairing defective cells in memory by comparing numbers of defective cells to determine if repair is required |
| 02/22/2001 | DE10026993A1 Semiconductor memory device e.g. EEPROM, has write-in driver circuit that substitutes the defect data in primary row with the data of secondary row selected by redundancy selector |
| 02/21/2001 | EP1077450A2 NAND type nonvolatile memory |
| 02/21/2001 | CN1285073A Circuit and method for testing a digital semi-conductor circuit |
| 02/21/2001 | CN1284724A Programmable data mode generator for use in chip of semiconductor memory |
| 02/20/2001 | US6192495 On-board testing circuit and method for improving testing of integrated circuits |
| 02/20/2001 | US6192487 Method and system for remapping physical memory |
| 02/20/2001 | US6192486 Memory defect steering circuit |
| 02/20/2001 | US6191987 Semiconductor memory test circuit |
| 02/20/2001 | US6191986 Memory device with redundancy arrays |
| 02/20/2001 | US6191985 Dynamic memory having two modes of operation |
| 02/20/2001 | US6191984 Redundancy circuit capable of disabling use of redundant memory cells that are defective |
| 02/20/2001 | US6191983 Semiconductor memory |
| 02/20/2001 | US6191982 Address comparing for non-precharged redundancy address matching with redundancy disable mode |
| 02/15/2001 | DE10024297A1 Semiconducting memory device has replacement word lines with minimum distance between replacement word lines greater than minimum distance between normal word lines |
| 02/14/2001 | EP0486295B1 Semiconductor memory device with redundant circuit |
| 02/13/2001 | US6189119 Semiconductor memory device having test mode |
| 02/13/2001 | US6188631 Semiconductor memory device column select circuit and method for minimizing load to data input/output lines |
| 02/13/2001 | US6188622 Method of identifying a defect within a memory circuit |
| 02/13/2001 | US6188621 Test circuit for flash memory device and method thereof |
| 02/13/2001 | US6188620 Semiconductor memory device having a redundancy judgment circuit |
| 02/13/2001 | US6188619 Memory device with address translation for skipping failed memory blocks |
| 02/13/2001 | US6188618 Semiconductor device with flexible redundancy system |
| 02/13/2001 | US6188617 Reundancy circuit for semiconductor memories |
| 02/13/2001 | US6188603 Nonvolatile memory device |
| 02/13/2001 | US6188597 Semiconductor memory having sub-select lines cross-connected to sub-decoders |
| 02/13/2001 | US6188057 Method and apparatus for testing photo-receiver arrays and associated read channels |
| 02/08/2001 | WO2001009902A1 Method and circuit for the correction of memory errors |
| 02/08/2001 | DE10035137A1 Semiconducting memory has control signal generation circuit, set/reset circuit, column address decoder circuit, memory cell field, delay circuit that can alter/vary reset signal delay time |