| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 04/26/2001 | WO2001029668A1 Redundant dual bank architecture for a simultaneous operation flash memory |
| 04/26/2001 | US20010000449 Method for diagnosing memory, memory diagnostic circuit and semiconductor memory device |
| 04/26/2001 | DE19951048A1 Procedure for identification of integrated circuit by generation of faulty or erroneous memory cells within memory and identification of the circuit from the faulty memory cell pattern, with no need to hard-wire a serial number |
| 04/26/2001 | DE10043926A1 Non-volatile ferroelectric memory e.g. dynamic random access memory has row redundancy drive circuit to output inactive signal to main word-line driver, if error occurs in selected row address in main cell region |
| 04/25/2001 | EP1094471A2 Method for electronic component testing |
| 04/25/2001 | EP1094469A1 Device for sense signal evaluation from a capacitive ferroelectric memory cell |
| 04/25/2001 | EP1093586A1 Integrated circuit with improved synchronism for an external clock signal at a data output |
| 04/25/2001 | CN1292553A Method for writing electrically-erasable programmable ROM, equipment and system |
| 04/24/2001 | US6223311 Semiconductor memory device having deterioration determining function |
| 04/24/2001 | US6223308 Identification and verification of a sector within a block of mass STO rage flash memory |
| 04/24/2001 | US6223248 Circuits systems and methods for re-mapping memory row redundancy during two cycle cache access |
| 04/24/2001 | US6222781 Semiconductor integrated circuit device capable of externally applying power supply potential to internal circuit while restricting noise |
| 04/24/2001 | US6222211 Memory package method and apparatus |
| 04/21/2001 | CA2324055A1 Electronic component testing process |
| 04/19/2001 | WO2001009902A8 Method and circuit for the correction of memory errors |
| 04/19/2001 | DE4433504C2 Halbleiterspeichervorrichtung A semiconductor memory device |
| 04/19/2001 | DE19714952C2 Verwaltung von Speichermodulen Management of memory modules |
| 04/18/2001 | EP0730764B1 A fault tolerant queue system and method therefor |
| 04/18/2001 | CN1292151A Vertically integrated circuit system |
| 04/18/2001 | CN1291791A Metal wire fused wire structure possessing cavity body |
| 04/18/2001 | CN1291773A Semiconductor device |
| 04/17/2001 | US6219810 Intelligent binning for electrically repairable semiconductor chips |
| 04/17/2001 | US6219807 Semiconductor memory device having an ECC circuit |
| 04/17/2001 | US6219806 Method of executing test programs for semiconductor testing system |
| 04/17/2001 | US6219656 Memory integrity for meters |
| 04/17/2001 | US6219293 Method and apparatus for supplying regulated power to memory device components |
| 04/17/2001 | US6219289 Data writing apparatus, data writing method, and tester |
| 04/17/2001 | US6219287 Fail memory circuit and interleave copy method of the same |
| 04/17/2001 | US6219286 Semiconductor memory having reduced time for writing defective information |
| 04/17/2001 | US6219285 Semiconductor storage device with synchronized selection of normal and redundant columns |
| 04/17/2001 | US6219282 Flash EPROM having means for increasing the reliability of stored data |
| 04/17/2001 | CA2203782C Semiconductor test chip with on-wafer switching matrix |
| 04/12/2001 | DE10048372A1 Address control circuit has selection clock signal, generator of address conversion data for converting test object addresses to memory addresses, conversion data memory, address converter |
| 04/12/2001 | DE10019790A1 Semiconductor memory test system computes relief solution by transmitting test data to workstation, if relief rescue of memory is detected by repair analysis |
| 04/10/2001 | US6216248 Integrated memory |
| 04/10/2001 | US6216247 32-bit mode for a 64-bit ECC capable memory subsystem |
| 04/10/2001 | US6216241 Method and system for testing multiport memories |
| 04/10/2001 | US6216240 Merged memory and logic (MML) integrated circuits including memory test controlling circuits and methods |
| 04/10/2001 | US6216239 Testing method and apparatus for identifying disturbed cells within a memory cell array |
| 04/10/2001 | US6216236 Processing unit for a computer and a computer system incorporating such a processing unit |
| 04/10/2001 | US6216186 Modular computer system including compatibility evaluation logic |
| 04/10/2001 | US6215723 Semiconductor memory device having sequentially disabling activated word lines |
| 04/10/2001 | US6215715 Integrated circuit memories including fuses between a decoder and a memory array for disabling defective storage cells in the memory array |
| 04/10/2001 | US6215712 Semiconductor memory device capable of multiple word-line selection and method of testing same |
| 04/10/2001 | US6215699 Nonvolatile semiconductor storage device having main block and redundancy block formed on different wells |
| 04/10/2001 | US6215351 Fuse-latch circuit |
| 04/10/2001 | US6215345 Semiconductor device for setting delay time |
| 04/10/2001 | US6215173 Redundancy fuse block having a small occupied area |
| 04/05/2001 | WO2001024185A1 Method and circuit for evaluating the information content of a memory cell |
| 04/05/2001 | DE19947041A1 Integrated dynamic semiconducting memory with redundant units of memory cells enables high quality of memory wrt. holding time of cell contents, low test and repair costs |
| 04/04/2001 | EP1089339A2 Ferroelectric capacitor and ferrroelectric memory |
| 04/04/2001 | EP1089293A1 Memory test method and nonvolatile memory with low error masking probability |
| 04/04/2001 | EP1089292A1 Nonvolatile memory and high speed memory test method |
| 04/04/2001 | EP1089085A1 Data shift register |
| 04/04/2001 | EP1089084A1 On-line testing of the programmable interconnect network in field programmable gate arrays |
| 04/04/2001 | EP1088311A1 Electronic test memory device |
| 04/04/2001 | EP1088274A1 Verification of compatibility between modules |
| 04/04/2001 | EP0902924B1 Redundancy memory circuit with rom storage cells |
| 04/03/2001 | US6212648 Memory module having random access memories with defective addresses |
| 04/03/2001 | US6212482 Circuit and method for specifying performance parameters in integrated circuits |
| 04/03/2001 | US6212118 Semiconductor memory |
| 04/03/2001 | US6212115 Test method for contacts in SRAM storage circuits |
| 04/03/2001 | US6212114 Methods of identifying defects in an array of memory cells and related integrated circuitry |
| 04/03/2001 | US6212113 Semiconductor memory device input circuit |
| 04/03/2001 | US6212112 Method to verify the integrity of the decoding circuits of a memory |
| 04/03/2001 | US6212107 Charge pump circuit and a step-up circuit provided with same |
| 04/03/2001 | US6212092 Semiconductor integrated circuit |
| 04/03/2001 | US6212090 Semiconductor device including a repetitive pattern |
| 04/03/2001 | US6211726 Low voltage, high-current electronic load |
| 04/03/2001 | US6211692 Method and apparatus for determining the robustness and incident angle sensitivity of memory cells to alpha-particle/cosmic ray induced soft errors |
| 03/29/2001 | WO2001022426A1 Apparatus and method for testing ferroelectric memories |
| 03/29/2001 | WO2001022225A1 Method and circuit configuration for storing data words in a ram module |
| 03/29/2001 | DE10033519A1 Integrated circuit has address converter that generates address of selected memory device, and data generator that generates data signal that is sent to selected memory device, based on clock signal |
| 03/28/2001 | EP1087405A1 Semiconductor memory device capable of generating offset voltage independent of bit line voltage |
| 03/28/2001 | EP1087404A2 Method, system and apparatus for determining that a programming voltage level is sufficient for reliably programming an EEPROM |
| 03/28/2001 | EP0783170B1 Apparatus and method for the acquisition and analysis of a three-dimensional distribution of discrete points |
| 03/28/2001 | CN1289445A Fuse circuit having zero power draw for partially blown condition |
| 03/27/2001 | US6208583 Synchronous semiconductor memory having an improved reading margin and an improved timing control in a test mode |
| 03/27/2001 | US6208578 Partial replacement of partially defective memory devices |
| 03/27/2001 | US6208572 Semiconductor memory device having resistive bitline contact testing |
| 03/27/2001 | US6208570 Redundancy test method for a semiconductor memory |
| 03/27/2001 | US6208569 Method of and apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device |
| 03/27/2001 | US6208568 Circuit for cancelling and replacing redundant elements |
| 03/27/2001 | US6208562 Digital memory and method of operation for a digital memory |
| 03/27/2001 | US6208552 Circuit and method for biasing the charging capacitor of a semiconductor memory array |
| 03/27/2001 | US6208547 Memory circuit/logic circuit integrated device capable of reducing term of works |
| 03/27/2001 | CA2205733C Method and apparatus of redundancy for non-volatile memory integrated circuits |
| 03/22/2001 | WO2001020615A1 High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes |
| 03/22/2001 | WO2001020614A1 Method of testing a memory |
| 03/22/2001 | WO2001020613A1 Circuit and method for column redundancy for high bandwidth memories |
| 03/22/2001 | WO2001020610A1 Architecture, method(s) and circuitry for low power memories |
| 03/22/2001 | WO2001020454A1 Memory redundancy techniques |
| 03/22/2001 | WO2001008161A3 A method and a device for testing a memory array in which fault response is compresed |
| 03/22/2001 | DE19944036A1 Integrierter Speicher mit wenigstens zwei Plattensegmenten Integrated memory having at least two plate segments |
| 03/22/2001 | DE19911939C2 Verfahren für den eingebauten Selbsttest einer elektronischen Schaltung Procedures for built-in self test of an electronic circuit |
| 03/22/2001 | CA2384862A1 Architecture, method(s) and circuitry for low power memories |
| 03/21/2001 | EP1085524A1 Structure and method with which to generate data background patterns for testing random-access-memories |
| 03/21/2001 | EP1085523A1 Integrated memory with memory cells and reference cells |
| 03/21/2001 | EP1085517A2 Integrated memory circuit with at least two plate segments |
| 03/21/2001 | EP1084497A1 On-chip circuit and method for testing memory devices |