| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 06/07/2001 | WO2001041149A1 Semiconductor storage and method for testing the same |
| 06/07/2001 | WO2001040947A1 Fuse latch having multiplexers with reduced sizes and lower power consumption |
| 06/07/2001 | US20010003196 Semiconductor integrated circuit having self-diagnosis test function and test method thereof |
| 06/07/2001 | US20010003051 Having logic circuit connected to external terminals, built-in memory connected to logic circuit, and burn-in test circuit for, when performing burn-in test, writing predetermined data into said built-in memory |
| 06/07/2001 | US20010002889 Method of stressing a memory device |
| 06/07/2001 | US20010002888 Method of testing a memory cell |
| 06/07/2001 | US20010002887 Electronic memory device |
| 06/07/2001 | US20010002883 Semiconductor device including a repetitive pattern |
| 06/07/2001 | DE10058030A1 Integrated circuit e.g. read only memory, has several non-volatile memory locations to store certain data set and has logic to calculate test code |
| 06/06/2001 | EP1104579A1 Memory supervision |
| 06/06/2001 | EP1104565A1 Integrated storage with inter-block redundancy |
| 06/05/2001 | US6243840 Self-test ram using external synchronous clock |
| 06/05/2001 | US6243839 Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns |
| 06/05/2001 | US6243795 Redundant, asymmetrically parallel disk cache for a data storage system |
| 06/05/2001 | US6243309 Semiconductor memory device having parallel test mode for simultaneously testing multiple memory cells |
| 06/05/2001 | US6243307 Semiconductor device including tester circuit suppressible of circuit scale increase and testing device of semiconductor device |
| 06/05/2001 | US6243306 Defect management engine for generating a unified address to access memory cells in a primary and a redundancy memory array |
| 06/05/2001 | US6243305 Memory redundancy device and method |
| 06/05/2001 | US6243301 Semiconductor memory device and signal line switching circuit |
| 05/31/2001 | US20010002461 Circuit and method for specifying performance parameters in integrated circuits |
| 05/31/2001 | US20010002176 Semiconductor memory device having a large band width and allowing efficient execution of redundant repair |
| 05/31/2001 | US20010002175 Semiconductor memory device having function of supplying stable power supply voltage |
| 05/31/2001 | US20010002174 Plash EEprom system |
| 05/31/2001 | US20010002112 Method and apparatus for the replacement of non-operational metal lines in DRAMS |
| 05/31/2001 | DE19957124A1 Testing memory cells with hysteresis curve e.g. for FRAM |
| 05/31/2001 | DE19956069A1 Integrierter Speicher mit Speicherzellen und Referenzzellen Integrated memory having memory cells and reference cells |
| 05/31/2001 | DE19954345A1 Speichereinrichtung Memory device |
| 05/30/2001 | CN1297231A Distributed measurement of memory array bit unit threshold voltage in line |
| 05/30/2001 | CN1297229A Optical disc device and data reading method |
| 05/29/2001 | US6240537 Signature compression circuit and method |
| 05/29/2001 | US6240535 Device and method for testing integrated circuit dice in an integrated circuit module |
| 05/29/2001 | US6240532 Programmable hit and write policy for cache memory test |
| 05/29/2001 | US6240525 Method and apparatus for re-addressing defective memory cells |
| 05/29/2001 | US6240033 Antifuse circuitry for post-package DRAM repair |
| 05/29/2001 | US6240029 Memory column redundancy |
| 05/29/2001 | US6240014 Semiconductor memory device |
| 05/29/2001 | US6239650 Low power substrate bias circuit |
| 05/29/2001 | US6239611 Circuit and method for testing whether a programmable logic device complies with a zero-hold-time requirement |
| 05/23/2001 | EP1102168A2 Integrated memory with memory cells and reference cells |
| 05/23/2001 | EP0928484B1 Charge sharing detection circuit for anti-fuses |
| 05/23/2001 | EP0786780B1 Data output control circuit of semiconductor memory device having pipeline structure |
| 05/23/2001 | EP0665558B1 Method for programming and testing a non-volatile memory |
| 05/23/2001 | EP0591811B1 Dynamic random access memory device having a parallel testing mode for producing arbitrary test pattern |
| 05/23/2001 | DE19954346A1 Memory device arrangement for 16-bit data storage |
| 05/23/2001 | DE10043191A1 Non-volatile ferroelectric memory has column redundancy selection circuit that omits failed column address of main cell array block by replacing column with column of redundancy cell array block |
| 05/23/2001 | DE10022698A1 Halbleiterspeichereinrichtung A semiconductor memory device |
| 05/23/2001 | CN1296266A Memory |
| 05/22/2001 | USRE37184 Semiconductor memory and screening test method thereof |
| 05/22/2001 | US6237123 Built-in self-test controlled by a token network and method |
| 05/22/2001 | US6237122 Semiconductor memory device having scan flip-flops |
| 05/22/2001 | US6237115 Design for testability in very high speed memory |
| 05/22/2001 | US6237110 Apparatus and method accessing flash memory |
| 05/22/2001 | US6236615 Semiconductor memory device having memory cell blocks different in data storage capacity without influence on peripheral circuits |
| 05/22/2001 | US6236602 Dynamic configuration of storage arrays |
| 05/22/2001 | US6236601 Semiconductor memory device having faulty cells |
| 05/22/2001 | US6236599 Repair signal generating circuit |
| 05/22/2001 | US6236241 Redundant decoder having fuse-controlled transistor |
| 05/22/2001 | US6236228 Structure and method of repair of integrated circuits |
| 05/22/2001 | US6235622 Method and apparatus for isolating a conductive region from a substrate during manufacture of an integrated circuit and connected to the substrate after manufacture |
| 05/17/2001 | US20010001326 Intelligent binning for electrically repairable semiconductor chips |
| 05/17/2001 | DE10027003A1 Halbleiterschaltungsvorrichtung mit der Fähigkeit, Stromversorgungspotentiale extern an eine interne Schaltung anzulegen und dabei Rauschen einzuschränken Semiconductor integrated circuit device with the ability to create electricity supply potentials external to an internal circuit and thereby reduce noise |
| 05/16/2001 | EP1100016A2 Memory device with replacement memory cells |
| 05/16/2001 | EP1099953A2 Semiconductor device with testing capability |
| 05/16/2001 | EP1099224A2 Circuit for generating a reference voltage for reading out from a ferroelectric memory |
| 05/16/2001 | CN1295333A Semiconductor integrated circuit device capable of inhibiting noise and supplying power potential |
| 05/15/2001 | US6233717 Multi-bit memory device having error check and correction circuit and method for checking and correcting data errors therein |
| 05/15/2001 | US6233705 Test method for data storage characteristics of memory |
| 05/15/2001 | US6233669 Memory address generator capable of row-major and column-major sweeps |
| 05/15/2001 | US6233183 Semiconductor memory device with high data access speed |
| 05/15/2001 | US6233182 Semiconductor integrated circuit and method for testing memory |
| 05/15/2001 | US6233181 Semiconductor memory device with improved flexible redundancy scheme |
| 05/10/2001 | WO2001033572A1 Efficient redundancy calculation system and method for various types of memory devices |
| 05/10/2001 | WO2001033237A1 Method and apparatus for testing circuits with multiple clocks |
| 05/10/2001 | WO2001033236A1 Multi-stage algorithmic pattern generator for testing ic chips |
| 05/10/2001 | US20010000992 Methods for forming and programming aligned fuses disposed in an integrated circuit |
| 05/10/2001 | DE10022697A1 Dynamic random access memory outputs test-mode-entry signal in response to address key, if write-enable and column-address-trigger signals are output before activation of row address trigger signal |
| 05/09/2001 | EP1097460A2 Integrated circuit comprising a self-test device for executing a self-test of the integrated circuit |
| 05/09/2001 | EP1097459A1 Memory circuit |
| 05/09/2001 | EP0721645B1 Automatic test circuitry with non-volatile status write |
| 05/08/2001 | US6230292 Devices and method for testing cell margin of memory devices |
| 05/08/2001 | US6230290 Method of self programmed built in self test |
| 05/08/2001 | US6230234 Direct logical block addressing flash memory mass storage architecture |
| 05/08/2001 | US6229741 Semiconductor integrated circuit device |
| 05/08/2001 | US6229728 Ferroelectric memory and method of testing the same |
| 05/08/2001 | US6228666 Method of testing integrated circuit including a DRAM |
| 05/03/2001 | WO2001031356A1 High-speed failure capture apparatus and method for automatic test equipment |
| 05/03/2001 | US20010000690 Semiconductor device with flexible redundancy system |
| 05/02/2001 | EP1096504A1 Content addressable memory having read/write capabilities that do not interrupt continuous search cycles |
| 05/01/2001 | US6226766 Method and apparatus for built-in self-test of smart memories |
| 05/01/2001 | US6226764 Integrated circuit memory devices including internal stress voltage generating circuits and methods for built-in self test (BIST) |
| 05/01/2001 | US6226221 Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts |
| 05/01/2001 | US6226211 Merged memory-logic semiconductor device having a built-in self test circuit |
| 05/01/2001 | US6226210 Method of detecting a short from a digit line pair to ground |
| 05/01/2001 | US6226209 Semiconductor memory device |
| 05/01/2001 | US6226202 Flash memory card including CIS information |
| 05/01/2001 | US6226200 In-circuit memory array bit cell threshold voltage distribution measurement |
| 05/01/2001 | US6225836 Semiconductor integrated circuit device capable of altering an operating mode by an electrical input applied from outside product package |
| 05/01/2001 | US6225655 Ferroelectric transistors using thin film semiconductor gate electrodes |
| 04/26/2001 | WO2001029843A2 Method for identifying an integrated circuit |
| 04/26/2001 | WO2001029840A1 Device for analysis of a signal from a ferroelectric storage capacitor |