| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 08/09/2001 | US20010013104 Loosely coupled mass storage computer cluster |
| 08/09/2001 | US20010012231 Memory circuit/logic circuit integrated device capable of reducing term of works |
| 08/09/2001 | US20010012221 Timing fuse option for row repair |
| 08/09/2001 | US20010012220 Method and apparatus for supplying regulated power to memory device components |
| 08/09/2001 | US20010012216 Semiconductor memory device for effecting erasing operation in block unit |
| 08/09/2001 | US20010011904 Integrated circuit having a self-test device for carrying out a self-test of the integrated circuit |
| 08/09/2001 | DE10004958A1 Information memory refresh device testing method - verifies initial condition of each selected memory cell before switching cell condition using test cycle of resetting memory and subsequent verification of new memory cell conditions |
| 08/08/2001 | EP1122742A2 Method for testing the refresh circuitry of a data memory |
| 08/08/2001 | CN1307361A Service signal generating circuit |
| 08/08/2001 | CN1307341A Integrated circuit semiconductor device and self-repairing circuit and method for built-in storage |
| 08/07/2001 | US6272655 Method of reducing test time for NVM cell-based FPGA |
| 08/07/2001 | US6272637 Systems and methods for protecting access to encrypted information |
| 08/07/2001 | US6272588 Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry |
| 08/07/2001 | US6272577 Data processing system with master and slave devices and asymmetric signal swing bus |
| 08/07/2001 | US6272068 Integrated circuit memory devices that utilize data masking techniques to facilitate test mode analysis |
| 08/07/2001 | US6272066 Synchronous semiconductor memory device capable of high speed reading and writing |
| 08/07/2001 | US6272061 Semiconductor integrated circuit device having fuses and fuse latch circuits |
| 08/07/2001 | US6272058 Semiconductor memory device capable of performing data reading/writing in units of plurality of bits |
| 08/07/2001 | US6272057 Semiconductor memory device |
| 08/07/2001 | US6272056 Semiconductor memory device capable of implementing redundancy-based repair efficiently in relation to layout and operating speed and semiconductor integrated circuit device having such semiconductor memory device |
| 08/07/2001 | US6271692 Semiconductor integrated circuit |
| 08/07/2001 | US6271571 Uprom memory cells for non-volatile memory devices integrated on semiconductors |
| 08/02/2001 | WO2001056160A1 Variable logical circuit, semiconductor integrated circuit, and method for manufacturing semiconductor integrated circuit |
| 08/02/2001 | WO2001056038A1 Semiconductor system |
| 08/02/2001 | US20010010656 Sequentially addressing a nonvolatile writeable memory device |
| 08/02/2001 | US20010010653 Semiconductor integrated circuit and method for adjusting characteristics of the same |
| 08/02/2001 | US20010010652 Semiconductor memory device capable of reducing data test time in pipeline |
| 08/02/2001 | US20010010651 Semiconductor integrated circuit |
| 08/02/2001 | DE10102405A1 Halbleiterspeicherbauelement mit datenübertragender Pipeline A semiconductor memory device having data-transferring pipeline |
| 08/02/2001 | DE10050363A1 Schaltung zum Erzeugen eines Reparatursignals Circuit for generating a repair signal |
| 08/02/2001 | DE10047176A1 Halbleiterspeicheranordnung, welche mit einer Erzeugungseinrichtung für ein internes Taktsignal für eine spezielle Betriebsart ausgestattet ist A semiconductor memory device, which is equipped with a device for generating an internal clock signal for a particular operating mode |
| 08/02/2001 | DE10042622A1 Halbleitervorrichtung mit einem Testmodus und Halbleitertestverfahren, welches dieselbe benutzt A semiconductor device having a test mode and semiconductor test method using the same |
| 08/02/2001 | DE10002139A1 Datenspeicher Data storage |
| 08/02/2001 | DE10002127A1 Testverfahren für einen Datenspeicher Test method for a data memory |
| 08/01/2001 | EP0927422B1 Method and apparatus for providing external access to internal integrated circuit test circuits |
| 07/31/2001 | US6269462 Selectable sense amplifier delay circuit and method |
| 07/31/2001 | US6269455 System and a method for processing information about locations of defective memory cells and a memory test with defect compression means |
| 07/31/2001 | US6269044 Semiconductor memory device employing an abnormal current consumption detection scheme |
| 07/31/2001 | US6269038 Semiconductor memory device with test mode decision circuit |
| 07/31/2001 | US6269037 Variable equilibrate voltage circuit for paired digit lines |
| 07/31/2001 | US6269036 System and method for testing multiple port memory devices |
| 07/31/2001 | US6269035 Circuit and method for a multiplexed redundancy scheme in a memory device |
| 07/31/2001 | US6269034 Semiconductor memory having a redundancy judgment circuit |
| 07/31/2001 | US6269033 Semiconductor memory device having redundancy unit for data line compensation |
| 07/31/2001 | US6269031 Semiconductor memory device |
| 07/31/2001 | US6269030 Semiconductor memory device |
| 07/31/2001 | US6269022 Threshold voltage setting circuit for reference memory cell and method for setting threshold voltage using the same |
| 07/31/2001 | US6268718 Burn-in test device |
| 07/31/2001 | US6268638 Metal wire fuse structure with cavity |
| 07/31/2001 | US6268623 Apparatus and method for margin testing single polysilicon EEPROM cells |
| 07/26/2001 | WO2001054135A1 Apparatus for testing memories with redundant storage elements |
| 07/26/2001 | WO2001054134A2 Test method for a data memory |
| 07/26/2001 | WO2001053944A2 Redundant data memory |
| 07/26/2001 | US20010010087 Method of analyzing fault occurring in semiconductor device |
| 07/26/2001 | US20010010086 Semiconductor memory device having deterioration determining function |
| 07/26/2001 | US20010009531 Memory device having a variable data output length |
| 07/26/2001 | US20010009530 Semiconductor memory device |
| 07/26/2001 | US20010009525 Word-line deficiency detection method for semiconductor memory device |
| 07/26/2001 | US20010009524 Semiconductor device having a test circuit |
| 07/26/2001 | US20010009523 Testing method and test apparatus in semiconductor apparatus |
| 07/26/2001 | US20010009522 Margin-range apparatus for a sense amp's voltage-pulling transistor |
| 07/26/2001 | US20010009521 Semiconductor memory device with improved flexible redundancy scheme |
| 07/26/2001 | US20010009519 Dynamic ram and semiconductor device |
| 07/26/2001 | US20010009276 Memory device having a variable data output length and a programmable register |
| 07/25/2001 | EP1118937A2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 07/24/2001 | US6266794 Circuit and method for testing an integrated circuit |
| 07/24/2001 | US6266792 Semiconductor memory, memory device, and memory card |
| 07/24/2001 | US6266755 Translation lookaside buffer with virtual address conflict prevention |
| 07/24/2001 | US6266749 Access time measurement circuit and method |
| 07/24/2001 | US6266725 Communications protocol for asynchronous memory card |
| 07/24/2001 | US6266626 ROM data verification circuit |
| 07/24/2001 | US6266287 Variable equilibrate voltage circuit for paired digit lines |
| 07/24/2001 | US6266286 Wafer burn-in test circuit and method for testing a semiconductor memory device |
| 07/24/2001 | US6266285 Method of operating a memory device having write latency |
| 07/24/2001 | US6266272 Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells |
| 07/24/2001 | CA2257740C Method and apparatus of column redundancy for non-volatile analog and multilevel memory integrated circuits |
| 07/19/2001 | US20010009029 Device and method for testing integrated circuit dice in an integrated circuit module |
| 07/19/2001 | US20010009022 Adaptive memory control |
| 07/19/2001 | US20010008494 Semiconductor memory |
| 07/19/2001 | US20010008488 Semiconductor integrated circuit |
| 07/19/2001 | US20010008382 Low current redundancy anti-fuse method and apparatus |
| 07/19/2001 | DE10064329A1 Fehleranalyseverfahren, Kompressionsschwellenwertableitungsverfahren und Aufzeichnungsmedium Fault analysis method, compression threshold derivation method and recording medium |
| 07/19/2001 | DE10063631A1 Virtual channel synchronized with a dynamic RAM for driving memory cells uses a semiconductor memory device with a base cell structure for a word driver, a main decoder and a reader booster for reading out information from the cells. |
| 07/18/2001 | EP1116241A2 A method and a device for testing a memory array in which fault response is compressed |
| 07/18/2001 | EP1116114A1 Technique for detecting memory part failures and single, double, and triple bit errors |
| 07/17/2001 | US6263460 Microcontroller architecture and associated method providing for testing of an on-chip memory device |
| 07/17/2001 | US6262935 Shift redundancy scheme for wordlines in memory circuits |
| 07/17/2001 | US6262928 Parallel test circuit and method for wide input/output DRAM |
| 07/17/2001 | US6262927 Current saturation test device |
| 07/17/2001 | US6262926 Nonvolatile semiconductor memory device |
| 07/17/2001 | US6262925 Semiconductor memory device with improved error correction |
| 07/17/2001 | US6262924 Programmable semiconductor memory device |
| 07/17/2001 | US6262923 Semiconductor memory device with redundancy function |
| 07/17/2001 | US6262916 Non-volatile semiconductor memory device capable of pre-conditioning memory cells prior to a data erasure |
| 07/17/2001 | US6261813 Two step enzymatic acylation |
| 07/12/2001 | WO2001050475A1 Usage of redundancy data for displaying failure bit maps for semiconductor devices |
| 07/12/2001 | WO2001050474A1 Method and apparatus for exercising external memory with a memory built-in self-test |
| 07/12/2001 | US20010007535 Redundancy method capable of disabling replacing redundant memory cells that are defective |
| 07/12/2001 | US20010007431 Low current redundancy anti-fuse method and apparatus |
| 07/12/2001 | DE19964012A1 Refreshing memory contents of read only memory cell involves comparing current memory cell charge state with threshold value above reading charge, raising charge state if below threshold |