| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 07/12/2001 | DE19963689A1 Schaltungsanordnung eines integrierten Halbleiterspeichers zum Speichern von Adressen fehlerhafter Speicherzellen Circuit arrangement of an integrated semiconductor memory for storing addresses of defective memory cells |
| 07/12/2001 | DE10054447A1 Semiconductor memory has cell-supply repair circuits and row decoder circuits respectively set between neighboring cell blocks, such that cell supply conductors are set between word lines of decoder circuits |
| 07/11/2001 | EP1115063A1 Non-volatile semiconductor memory device with error management |
| 07/11/2001 | EP0788116B1 Overvoltage detection circuit for mode selection |
| 07/11/2001 | CN1303103A Semi-conductor memory possessing high speed information packet data input |
| 07/11/2001 | CN1303101A Semi-conductor memory possessing test pattern decision circuit |
| 07/10/2001 | US6260097 Method and apparatus for controlling a synchronous memory device |
| 07/10/2001 | US6259647 Synchronous semiconductor memory device allowing easy and fast test |
| 07/10/2001 | US6259640 Semiconductor storage device having a delayed sense amplifier activating signal during a test mode |
| 07/10/2001 | US6259639 Semiconductor integrated circuit device capable of repairing defective parts in a large-scale memory |
| 07/10/2001 | US6259638 Integrated circuit memory devices having an improved wafer burn-in test capability through independent operational control of a memory cell array and related methods of testing same |
| 07/10/2001 | US6259637 Method and apparatus for built-in self-repair of memory storage arrays |
| 07/10/2001 | US6259636 Semiconductor memory device having redundancy circuit for relieving faulty memory cells |
| 07/10/2001 | US6259309 Method and apparatus for the replacement of non-operational metal lines in DRAMS |
| 07/10/2001 | US6259271 Configuration memory integrated circuit |
| 07/05/2001 | US20010006558 Failure analysis method, compression threshold deriving method, and recording medium |
| 07/05/2001 | US20010006481 Integrated semiconductor memory with a memory unit for storing addresses of defective memory cells |
| 07/05/2001 | US20010006351 Low current redundancy anti-fuse method and apparatus |
| 07/05/2001 | DE19962677A1 Anordnung zum Testen einer Vielzahl von Halbleiterchips An arrangement for testing a plurality of semiconductor chips |
| 07/05/2001 | DE19962234A1 Application specific integrated circuit with built-in self-testing |
| 07/05/2001 | DE10058464A1 Pattern generation method for use in testing semiconductor integrated circuit, involves generating desired pattern data based on logical value of each byte of juxtaposition pattern data |
| 07/04/2001 | EP1113454A2 Check method of temporary storage circuit in electronic control unit |
| 07/04/2001 | EP1113453A2 Memory circuit |
| 07/04/2001 | EP1113449A1 Semiconductor memory device having row-related circuit operating at high speed |
| 07/04/2001 | EP1113362A2 Integrated semiconductor memory with a memory unit for storing addresses of faulty memory cells |
| 07/04/2001 | EP1113282A2 System for testing a plurality of semiconductor chips |
| 07/04/2001 | EP1113280A2 Semiconductor integrated circuit having self-diagnosis test function and test method thereof |
| 07/04/2001 | EP1112577A1 Built-in self test schemes and testing algorithms for random access memories |
| 07/04/2001 | EP0965083B1 Memory with redundancy circuit |
| 07/03/2001 | US6256762 Semiconductor disk device |
| 07/03/2001 | US6256757 Apparatus for testing memories with redundant storage elements |
| 07/03/2001 | US6256756 Embedded memory bank system |
| 07/03/2001 | US6256755 Apparatus and method for detecting defective NVRAM cells |
| 07/03/2001 | US6256754 Memory system having internal state monitoring circuit |
| 07/03/2001 | US6256749 Disk array system and its control method |
| 07/03/2001 | US6256703 Adaptive memory control |
| 07/03/2001 | US6256702 Nonvolatile memory device with extended storage and high reliability through writing the same data into two memory cells |
| 07/03/2001 | US6256257 Memory device including a burn-in controller for enabling multiple wordiness during wafer burn-in |
| 07/03/2001 | US6256243 Test circuit for testing a digital semiconductor circuit configuration |
| 07/03/2001 | US6256242 Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
| 07/03/2001 | US6256241 Short write test mode for testing static memory cells |
| 07/03/2001 | US6256240 Semiconductor memory circuit |
| 07/03/2001 | US6256239 Redundant decision circuit for semiconductor memory device |
| 07/03/2001 | US6256238 Semiconductor memory device |
| 07/03/2001 | US6256237 Semiconductor device and method for repairing failed memory cell by directly programming fuse memory cell |
| 07/03/2001 | US6255895 Circuit for generating a reference voltage trimmed by an anti-fuse programming |
| 07/03/2001 | US6255894 Low current redundancy anti-fuse method and apparatus |
| 07/03/2001 | US6255835 Circuit for testing option of a semiconductor memory device |
| 06/28/2001 | WO2000077529A3 Method and apparatus for testing a video display chip |
| 06/28/2001 | US20010005896 On-board testing circuit and method for improving testing of integrated circuits |
| 06/28/2001 | US20010005373 Virtual channel DRAM |
| 06/28/2001 | US20010005335 Row redundancy circuit using a fuse box independent of banks |
| 06/28/2001 | US20010005144 Configuration for testing a multiplicity of semiconductor chips |
| 06/28/2001 | US20010005132 Semiconductor device testing method and system and recording medium |
| 06/28/2001 | US20010005027 Semiconductor memory circuit |
| 06/28/2001 | US20010005014 Semiconductor storage device having redundancy circuit for replacement of defect cells under tests |
| 06/28/2001 | US20010005013 Semiconductor integrated circuit and integrated circuit system |
| 06/27/2001 | EP1111618A1 Read/write protected electrical fuse architecture |
| 06/27/2001 | CN1067795C 半导体集成电路器件 The semiconductor integrated circuit device |
| 06/27/2001 | CN1067779C Method for preventing computer from presenting non-accessed data |
| 06/26/2001 | US6253281 Method for updating firmware of a computer peripheral device |
| 06/26/2001 | US6252820 Semiconductor memory device capable of monitoring and adjusting the timing and pulse width of internal control signals |
| 06/26/2001 | US6252812 Semiconductor memory device utilizing multiple edges of a signal |
| 06/26/2001 | US6252811 Method and apparatus for testing memory devices |
| 06/26/2001 | US6252810 Circuit and method for detecting defects in semiconductor memory |
| 06/26/2001 | US6252809 Semiconductor memory device capable of easily determining locations of defective memory cells by selectively isolating and testing redundancy memory cell block |
| 06/26/2001 | US6252808 Semiconductor memory device having improved row redundancy scheme and method for curing defective cell |
| 06/26/2001 | US6252805 Semiconductor memory device including programmable output pin determining unit and method of reading the same during test mode |
| 06/26/2001 | US6252800 Semiconductor memory device |
| 06/21/2001 | US20010004333 Method of compensating for a defect within a semiconductor device |
| 06/21/2001 | US20010004331 Semiconductor storage device |
| 06/21/2001 | US20010004326 Memory controller for flash memory system and method for writing data to flash memory device |
| 06/20/2001 | EP1109172A1 In-circuit memory array bit cell thereshold voltage distribution measurement |
| 06/19/2001 | US6249893 Method and structure for testing embedded cores based system-on-a-chip |
| 06/19/2001 | US6249889 Method and structure for testing embedded memories |
| 06/19/2001 | US6249478 Address input circuit and semiconductor memory using the same |
| 06/19/2001 | US6249468 Semiconductor memory device with switching element for isolating bit lines during testing |
| 06/19/2001 | US6249466 Row redundancy scheme |
| 06/19/2001 | US6249465 Redundancy programming using addressable scan paths to reduce the number of required fuses |
| 06/19/2001 | US6249464 Block redundancy in ultra low power memory circuits |
| 06/19/2001 | US6249457 Nonvolatile memory device and inspection method therefor |
| 06/14/2001 | WO2001043141A1 Semiconductor memory testing device |
| 06/14/2001 | WO2001042803A2 Bit fail map compression with fail signature analysis |
| 06/14/2001 | US20010003509 Non-volatile semiconductor memory |
| 06/13/2001 | EP1107121A2 Non-volatile semiconductor memory with programmable latches |
| 06/13/2001 | EP1105876A1 Method and apparatus for built-in self test of integrated circuits |
| 06/13/2001 | EP1105802A1 Method for repairing faulty storage cells of an integrated memory |
| 06/13/2001 | EP0675501B1 Non-volatile memory element with double programmable cell and corresponding reading circuit for redundancy circuits |
| 06/13/2001 | EP0551009B1 Method for synchronizing reserved areas in a redundant storage array |
| 06/13/2001 | DE19937062C1 Digital circuit with boundary scan cell with memory unit ensures that digital units can be tested without electrical access, with control and observation of signal connections |
| 06/13/2001 | CN1299137A Integrated circuit testing device |
| 06/12/2001 | US6247153 Method and apparatus for testing semiconductor memory device having a plurality of memory banks |
| 06/12/2001 | US6246623 Method and apparatus for strobing antifuse circuits in a memory device |
| 06/12/2001 | US6246622 Semiconductor memory device |
| 06/12/2001 | US6246619 Self-refresh test time reduction scheme |
| 06/12/2001 | US6246618 Semiconductor integrated circuit capable of testing and substituting defective memories and method thereof |
| 06/12/2001 | US6246617 Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device |
| 06/12/2001 | US6246616 Memory device having redundancy cells |
| 06/12/2001 | US6246615 Redundancy mapping in a multichip semiconductor package |
| 06/07/2001 | WO2001041150A2 Architecture with multi-instance redundancy implementation |