| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 09/04/2001 | US6285621 Method of minimizing the access time in semiconductor memories |
| 09/04/2001 | US6285620 Semiconductor device and method for repairing failed memory cell by directly programming fuse memory cell |
| 09/04/2001 | US6285618 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array |
| 09/04/2001 | US6285610 Burn-in test circuit |
| 09/04/2001 | US6285609 Method and apparatus for testing memory devices |
| 09/04/2001 | US6285608 Method and apparatus for using supply voltage for testing in semiconductor memory devices |
| 09/04/2001 | US6285607 Memory system |
| 09/04/2001 | US6285606 Semiconductor memory device |
| 09/04/2001 | US6285605 Integrated memory having redundant units of memory cells, and test method for the redundant units |
| 09/04/2001 | US6285603 Repair circuit of semiconductor memory device |
| 09/04/2001 | US6285600 Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing |
| 08/30/2001 | WO2001063619A2 Method for efficient analysis of semiconductor failures |
| 08/30/2001 | WO2001063311A2 Method and system for wafer and device-level testing of an integrated circuit |
| 08/30/2001 | US20010017814 Semiconductor integrated circuit device with test interface circuit for performing test on embedded memory from outside |
| 08/30/2001 | US20010017811 Semiconductor memory device |
| 08/30/2001 | US20010017807 Semiconductor memory device allowing static-charge tolerance test between bit lines |
| 08/30/2001 | US20010017806 Method of repairing defective memory cells of an integrated memory |
| 08/30/2001 | US20010017804 Semiconductor device, semiconductor memory device and test-mode entry method |
| 08/30/2001 | US20010017803 Semiconductor memory |
| 08/30/2001 | US20010017802 Semiconductor device and semiconductor device testing method |
| 08/30/2001 | US20010017799 Efficient memory allocation scheme for data collection |
| 08/30/2001 | US20010017792 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other |
| 08/30/2001 | US20010017790 Synchronous semiconductor memeory device and method for reading data |
| 08/30/2001 | US20010017552 Semiconductor device and semiconductor device testing method |
| 08/30/2001 | US20010017546 Antifuse repair circuit |
| 08/30/2001 | US20010017380 Semiconductor integrated circuit |
| 08/30/2001 | US20010017368 Semiconductor memory devices and methods for sampling data therefrom based on a relative position of a memory cell array section containing the data |
| 08/30/2001 | DE10007604A1 Redundanz-Multiplexer für Halbleiterspeicheranordnung Redundancy multiplexer for semiconductor memory device |
| 08/30/2001 | DE10005618A1 Integrierter Halbleiterspeicher mit redundanter Einheit von Speicherzellen Integrated semiconductor memory with a redundant unit of the memory cells |
| 08/29/2001 | EP1128391A1 A method and a circuit architecture for testing an integrated circuit comprising a programmable, non-volatile memory |
| 08/29/2001 | EP1128269A2 Method for addressing electrical fuses |
| 08/29/2001 | EP1128268A2 Redundancy multiplexer for semiconductor memory device |
| 08/29/2001 | EP1055238B1 Circuit and method for testing a digital semi-conductor circuit |
| 08/29/2001 | CN2445549Y Packaging structure of memory chip or module |
| 08/29/2001 | CN1310847A Electronic test memory device |
| 08/29/2001 | CN1310449A Semi-conductor storage apparatus with displacement program circuit |
| 08/28/2001 | US6282689 Error correction chip for memory applications |
| 08/28/2001 | US6282622 System, method, and program for detecting and assuring DRAM arrays |
| 08/28/2001 | US6282134 Memory test method and nonvolatile memory with low error masking probability |
| 08/28/2001 | US6282122 Evaluation of memory cell characteristics |
| 08/28/2001 | US6282121 Flash memory device with program status detection circuitry and the method thereof |
| 08/28/2001 | US6281739 Fuse circuit and redundant decoder |
| 08/28/2001 | US6281736 Method and circuitry for soft fuse row redundancy with simple fuse programming |
| 08/28/2001 | US6281716 Potential detect circuit for detecting whether output potential of potential generation circuit has arrived at target potential or not |
| 08/23/2001 | WO2001061572A2 An efficient memory allocation scheme for data collection |
| 08/23/2001 | US20010016928 Semiconductor memory, memory device, and memory card |
| 08/23/2001 | US20010016923 Program execution system for semiconductor testing apparatus |
| 08/23/2001 | US20010016893 Layout for a semiconductor memory device having redundant elements |
| 08/23/2001 | US20010015932 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 08/23/2001 | US20010015927 Synchronous semiconductor memory device having improved operational frequency margin at data input/output |
| 08/23/2001 | US20010015926 Semiconductor memory device and method for setting stress voltage |
| 08/23/2001 | US20010015925 Method and a circuit architecture for testing an integrate circuit comprising a programmable, non-volatile memory |
| 08/23/2001 | US20010015924 Test interface circuit and semiconductor integrated circuit device including the same |
| 08/23/2001 | US20010015921 Integrated memory with interblock redundancy |
| 08/23/2001 | US20010015908 Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory |
| 08/22/2001 | WO2002065291A2 Device for reconfiguring a faulty storage assembly |
| 08/22/2001 | EP1126475A2 Method and device for testing the SDRAM working memory of a personal computer |
| 08/22/2001 | EP1126474A1 Semiconductor memory device |
| 08/22/2001 | EP1126473A1 Semiconductor memory device |
| 08/22/2001 | EP1126472A1 Flash-erasable semiconductor memory device |
| 08/22/2001 | EP1126372A1 Non-volatile memory device with configurable row redundancy |
| 08/22/2001 | EP1125203A1 Column redundancy circuit with reduced signal path delay |
| 08/22/2001 | EP1125202A1 Storage device for storing data and method for operating storage devices for data storage |
| 08/22/2001 | CN1309299A Method for testing electronic element |
| 08/21/2001 | US6279141 Preburn-in dynamic random access memory module and preburn-in circuit board thereof |
| 08/21/2001 | US6279135 On-the-fly row-syndrome generation for DVD controller ECC |
| 08/21/2001 | US6279133 Method and apparatus for significantly improving the reliability of multilevel memory architecture |
| 08/21/2001 | US6279129 Configuration of memory cells and method of checking the operation of memory cells |
| 08/21/2001 | US6278652 Input initial stage circuit for semiconductor memory |
| 08/21/2001 | US6278643 Column redundancy for prefetch |
| 08/21/2001 | US6278642 Method and apparatus for limiting bitline current |
| 08/21/2001 | US6278285 Configuration for testing integrated components |
| 08/16/2001 | WO2001059790A1 Testable rom chip for a data memory redundant logic |
| 08/16/2001 | WO2001059789A1 Semiconductor integrated circuit device |
| 08/16/2001 | WO2001059571A2 Command-driven test modes |
| 08/16/2001 | WO2000077529B1 Method and apparatus for testing a video display chip |
| 08/16/2001 | US20010014959 Probeless testing of pad buffers on wafer |
| 08/16/2001 | US20010014923 Method for connecting caches in external storage subsystem |
| 08/16/2001 | US20010014043 MRAD test circuit, semiconductor memory device having the same and MRAD test method |
| 08/16/2001 | US20010014040 Semiconductor memory device having program circuit |
| 08/16/2001 | US20010014034 Nonvolatile semiconductor memory device |
| 08/16/2001 | US20010014030 Layout design method on semiconductor chip for avoiding detour wiring |
| 08/16/2001 | US20010013805 Low current redundancy anti -fuse apparatus |
| 08/16/2001 | EP1124232A2 Integrated semiconductor memory with redundant cells |
| 08/16/2001 | EP1123556A1 Fuse circuit having zero power draw for partially blown condition |
| 08/16/2001 | DE10103060A1 Verfahren zum Testen einer ein Floating-Gate aufweisenden Speicherzelle A method for testing a floating gate memory cell comprising |
| 08/16/2001 | DE10101067A1 Program execution system of semiconductor test device, has programs in processor which are written in exclusive and general purpose programming languages based on hardware for semiconductor examination |
| 08/16/2001 | DE10005312A1 Verfahren zum Auffinden der eigentlichen Ursache des Ausfalls eines fehlerhaften Chips A method for finding the root cause of the failure of a defective chip |
| 08/15/2001 | CN1308336A Memory device |
| 08/14/2001 | US6275963 Test circuit and a redundancy circuit for an internal memory circuit |
| 08/14/2001 | US6275961 Circuit and method for performing tests on memory array cells using external sense amplifier reference current |
| 08/14/2001 | US6275960 Self-test and correction of loss of charge errors in a flash memory, erasable and programmable by sectors thereof |
| 08/14/2001 | US6275443 Latched row or column select enable driver |
| 08/14/2001 | US6275442 Address decoder and method for ITS accelerated stress testing |
| 08/14/2001 | US6275436 Flash memory control method and apparatus processing system therewith |
| 08/14/2001 | US6275434 Semiconductor memory |
| 08/14/2001 | US6275428 Memory-embedded semiconductor integrated circuit device and method for testing same |
| 08/14/2001 | US6275427 Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under test |
| 08/14/2001 | US6275406 Content address memory circuit with redundant array and method for implementing the same |
| 08/09/2001 | US20010013110 On-chip circuit and method for testing memory devices |