| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 09/25/2001 | US6295618 Method and apparatus for data compression in memory devices |
| 09/25/2001 | US6295617 Testing method of semiconductor memory device and semiconductor memory device applicable to the method |
| 09/25/2001 | US6295595 Method and structure for accessing a reduced address space of a defective memory |
| 09/25/2001 | US6295591 Method of upgrading and/or servicing memory without interrupting the operation of the system |
| 09/25/2001 | US6295589 Apparatus and method prohibiting RAM diagnosis when other units may access RAM |
| 09/25/2001 | US6295243 Semiconductor device |
| 09/25/2001 | US6295239 Control apparatus for testing a random access memory |
| 09/25/2001 | US6295238 Semiconductor memory device having a circuit for fast operation |
| 09/25/2001 | US6295237 Semiconductor memory configuration with a built-in-self-test |
| 09/25/2001 | US6295236 Semiconductor memory of the random access type with a bus system organized in two planes |
| 09/25/2001 | US6295235 Redundancy circuit of semiconductor memory |
| 09/25/2001 | US6295228 System for programming memory cells |
| 09/25/2001 | US6294909 Electro-magnetic lithographic alignment method |
| 09/20/2001 | WO2001069794A1 Interleave address generator |
| 09/20/2001 | WO2001015172A3 Flash memory with externally triggered detection and repair of leaky cells |
| 09/20/2001 | US20010023491 Device for testing digital signal processor in digital video disc reproducing apparatus |
| 09/20/2001 | US20010023466 Memory device having a programmable register |
| 09/20/2001 | US20010023093 Semiconductor memory device employing row repair scheme |
| 09/20/2001 | US20010022752 Method and apparatus for rapidly testing memory devices |
| 09/20/2001 | US20010022751 Redundancy circuit of semiconductor memory |
| 09/20/2001 | US20010022750 Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device |
| 09/20/2001 | US20010022748 Virtual channel synchronous dynamic random access memory |
| 09/20/2001 | US20010022747 Semiconductor memory device and redundancy circuit, and method of increasing redundancy efficiency |
| 09/20/2001 | US20010022746 Memory repair circuit using antifuse of MOS structure |
| 09/20/2001 | US20010022744 Semiconductor memory device having a page latch circuit and a test method thereof |
| 09/20/2001 | US20010022743 Semiconductor integrated circuit device |
| 09/20/2001 | US20010022740 Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices |
| 09/20/2001 | DE10107427A1 Semiconductor memory device for computer, determines redundant memory cell address by referencing address in main memory corresponding to designated data in sub-memory for defect recovery |
| 09/19/2001 | EP1134659A2 Redundancy multiplexer for semiconductor memory device |
| 09/19/2001 | CN2449338Y Autoamtic burn-recording device for ROM |
| 09/18/2001 | US6292914 Semiconductor memory capable of verifying stored data |
| 09/18/2001 | US6292422 Read/write protected electrical fuse |
| 09/18/2001 | US6292421 Method and apparatus for multiple row activation in memory devices |
| 09/18/2001 | US6292414 Method for repairing defective memory cells of an integrated semiconductor memory |
| 09/18/2001 | US6292383 Redundant memory cell for dynamic random access memories having twisted bit line architectures |
| 09/18/2001 | US6292015 Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation |
| 09/18/2001 | US6292013 Column redundancy scheme for bus-matching fifos |
| 09/18/2001 | US6292008 Circuit configuration for burn-in systems for testing modules by using a board |
| 09/18/2001 | US6291844 Semiconductor memory device with an improved layout of programmable fuses |
| 09/13/2001 | WO2001067601A2 Test circuit configuration and method for testing a large number of transistors |
| 09/13/2001 | WO2001067463A1 A method and apparatus for diagnosing memory using self-testing circuits |
| 09/13/2001 | WO2001067461A1 Semiconductor memory |
| 09/13/2001 | WO2001067249A2 Address decoding system and method for failure tolerance in a memory bank |
| 09/13/2001 | WO2001067248A2 Digital memory circuit |
| 09/13/2001 | WO1997012366A3 Hard disk storage system with coupled disks |
| 09/13/2001 | US20010021988 Semiconductor testing apparatus for testing semiconductor device including built in self test circuit |
| 09/13/2001 | US20010021558 Semiconductor integrated circuit device |
| 09/13/2001 | US20010021143 Circuit, apparatus and method for generating address |
| 09/13/2001 | US20010021142 Synchronous semiconductor memory device allowing easy and fast test |
| 09/13/2001 | US20010021134 Integrated semiconductor memory with redundant units for memory cells |
| 09/13/2001 | US20010021132 Redundant multiplexer for a semiconductor memory configuration |
| 09/13/2001 | US20010021131 Semiconductor Device |
| 09/13/2001 | US20010021129 Semiconductor memory device with restrained scale of decoding circuit used in shift redundancy |
| 09/13/2001 | US20010021120 Ferroelectric memory |
| 09/13/2001 | US20010020889 Antifuse programming circuit |
| 09/13/2001 | US20010020728 Metal wire fuse structure with cavity |
| 09/12/2001 | EP1132925A2 Data path calibration and testing mode using a data bus for semiconductor memories |
| 09/12/2001 | EP1132924A2 Self-testing of magneto-resistive memory arrays |
| 09/12/2001 | EP1132922A1 Ferroelectric memory |
| 09/12/2001 | EP1131718A1 Levelizing transfer delays for a channel of memory devices in a memory subsystem |
| 09/12/2001 | EP1131716A1 Memory redundancy techniques |
| 09/12/2001 | EP1131645A1 A skew calibration means and method of skew calibration |
| 09/12/2001 | EP0834124B1 Parallel testing of cpu cache and instruction units |
| 09/12/2001 | EP0579366B1 Redundancy circuits for semiconductor memory devices |
| 09/11/2001 | US6289481 Multi-value type semiconductor memory device and its defect removal method |
| 09/11/2001 | US6289470 Data monitor circuit |
| 09/11/2001 | US6288969 Multi-port random access memory |
| 09/11/2001 | US6288965 Reference voltage generating circuit, semiconductor memory device and burn-in method therefor |
| 09/11/2001 | US6288963 Semiconductor memory device |
| 09/11/2001 | US6288958 Semiconductor storage device and burn-in test method |
| 09/11/2001 | US6288957 Semiconductor memory device having test mode and method for testing semiconductor therewith |
| 09/11/2001 | US6288956 Semiconductor device having test function |
| 09/11/2001 | US6288955 Methods and systems for testing integrated circuit memory devices by overlappiing test result loading and test result analysis |
| 09/11/2001 | US6288954 Integrated circuit having an on-board reference generator |
| 09/11/2001 | US6288950 Semiconductor memory device capable of generating offset voltage independent of bit line voltage |
| 09/11/2001 | US6288945 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 09/11/2001 | US6288944 NAND type nonvolatile memory with improved erase-verify operations |
| 09/11/2001 | US6288940 Non-volatile semiconductor memory device |
| 09/11/2001 | US6288939 Circuit configuration for monitoring states of a memory device |
| 09/11/2001 | US6288561 Method and apparatus for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus |
| 09/07/2001 | WO2001065605A1 Semiconductor device |
| 09/07/2001 | WO2000073905A3 Test interface for electronic circuits |
| 09/06/2001 | US20010019511 Semiconductor integrated circuit |
| 09/06/2001 | US20010019510 Method and device for refreshing the memory content of a memory cell of a read-only memory |
| 09/06/2001 | US20010019507 Redundancy multiplexer for a semiconductor memory configuration |
| 09/06/2001 | US20010019499 Semiconductor integrated circuit device |
| 09/06/2001 | US20010019284 Integrated circuit |
| 09/06/2001 | DE10008578A1 Redundanz-Multiplexer für Halbleiterspeicheranordnung Redundancy multiplexer for semiconductor memory device |
| 09/06/2001 | DE10007177A1 Working memory testing circuit and method for personal computer containing Synchronous Dynamic Random Access Memory uses additional inserted card |
| 09/05/2001 | EP1130517A1 Redundancy architecture for an interleaved memory |
| 09/05/2001 | EP1129454A1 Method of testing a memory |
| 09/05/2001 | EP1129415A1 Automatic generation of user definable memory bist circuitry |
| 09/05/2001 | EP0732701B1 Bit-line precharge current limiter for CMOS dynamic memories |
| 09/05/2001 | EP0629868B1 Flat panel display device and method of inspection of same |
| 09/04/2001 | US6286121 Semiconductor device |
| 09/04/2001 | US6286120 Memory architecture for automatic test equipment using vector module table |
| 09/04/2001 | US6286116 Built-in test method for content addressable memories |
| 09/04/2001 | US6286115 On-chip testing circuit and method for integrated circuits |
| 09/04/2001 | US6285962 Method and system for testing rambus memory modules |
| 09/04/2001 | US6285623 Semiconductor memory |