G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation

Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
12/2001
12/19/2001	EP1164381A2 Integrated circuit with a test fucntion and test arrangement for testing an integrated circuit
12/19/2001	EP1163680A1 Device and method for carrying out the built-in self-test of an electronic circuit
12/19/2001	EP1163679A1 Method of operating an integrated memory with writable memory cells and corresponding integrated memory
12/19/2001	EP1163584A1 Method and apparatus for memory redundancy with no critical delay-path
12/19/2001	CN1327595A Method for testing a memory array and with a fault response signal signaling mode based on memory
12/18/2001	US6332206 High-speed error correcting apparatus with efficient data transfer
12/18/2001	US6332183 Method for recovery of useful areas of partially defective synchronous memory components
12/18/2001	US6331962 Semiconductor device including voltage down converter allowing tuning in short period of time and reduction of chip area
12/18/2001	US6331958 Semiconductor memory device having data parallel/serial conversion function and capable of efficiently performing operational test
12/18/2001	US6331956 Synchronous semiconductor memory device having redundant circuit of high repair efficiency and allowing high speed access
12/18/2001	US6331954 Determination of misalignment for floating gates near a gate stack bending point in array of flash memory cells
12/18/2001	US6331949 Circuit for storing and latching defective address data for a nonvolatile semiconductor memory device having redundant function
12/13/2001	WO2001095339A2 High speed protocol memory test head for a memory tester
12/13/2001	WO2001095117A2 Data processing system for high speed memory test
12/13/2001	WO2001041150A3 Architecture with multi-instance redundancy implementation
12/13/2001	WO2001029843A3 Method for identifying an integrated circuit
12/13/2001	US20010052093 Memory testing method and memory testing apparatus
12/13/2001	US20010052090 Storage device having an error correction function
12/13/2001	US20010052039 Card-type recording medium and card-type recording medium reader
12/13/2001	US20010050876 Semiconductor memory device with bank configuration
12/13/2001	US20010050871 Semiconductor memory integrated circuit
12/13/2001	US20010050870 Semiconductor memory device
12/13/2001	US20010050868 Semiconductor memory device with redundancy circuit
12/13/2001	US20010050861 Nonvolatile semiconductor storage device and test method therefor
12/13/2001	US20010050578 Semiconductor apparatus
12/13/2001	US20010050573 Chip-on-chip testing using bist
12/13/2001	DE10115717A1 Memory redundant system uses a contents addressable memory to store addresses of defect cells
12/13/2001	DE10059667A1 Semiconductor memory device has word configuration selection stage that selects word configuration for normal mode from number of configurations if deactivated test mode signal input
12/13/2001	DE10026737A1 Module specific repair method of semiconductor memory, involves applying certain address of incorrect memory cell to all memory modules at same time, and selecting the module corresponding to that address, for repair
12/13/2001	DE10026654A1 Digitale Speicherschaltung Digital memory circuit
12/13/2001	DE10026275A1 Verfahren zum Testen einer Vielzahl von Wortleitungen einer Halbleiterspeicheranordnung A method for testing a plurality of word lines of a semiconductor memory arrangement
12/12/2001	EP1162747A2 Line segmentation in programmable logic devices having redundancy circuitry
12/12/2001	EP1162655A2 Integrated circuit device for testing of transistors and semiconductor wafer equipped with such a circuit device
12/12/2001	EP0933785B1 Semiconductor device and power supply current detecting method
12/12/2001	EP0642134B1 Test of a static random access memory
12/11/2001	US6330697 Apparatus and method for performing a defect leakage screen test for memory devices
12/11/2001	US6330696 Self-testing of DRAMs for multiple faults
12/11/2001	US6330693 Method and apparatus for testing memory devices and displaying results of such tests
12/11/2001	US6330688 On chip error correction for devices in a solid state drive
12/11/2001	US6330297 Semiconductor integrated circuit device capable of reading out chip-specific information during testing and evaluation
12/11/2001	US6330205 Virtual channel synchronous dynamic random access memory
12/11/2001	US6330203 Test mode for verification of on-chip generated row addresses
12/11/2001	US6330200 Synchronous semiconductor memory device having improved operational frequency margin at data input/output
12/11/2001	US6330199 Semiconductor memory device and redundancy circuit, and method of increasing redundancy efficiency
12/11/2001	US6330198 Semiconductor storage device
12/11/2001	US6329833 System and method for automatically measuring input voltage levels for integrated circuits
12/11/2001	US6329642 Semiconductor device and semiconductor chip
12/06/2001	WO2001093494A1 Error-correcting code adapted for memories that store multiple bits per storage cell
12/06/2001	WO2001093276A1 Redundancy analysis method and apparatus for memory testing
12/06/2001	WO2001093034A2 Dual-ported cams for a simultaneous operation flash memory
12/06/2001	US20010049807 Address generator of dynamic memory testing circuit and address generating method thereof
12/06/2001	US20010049805 Circuit, system and method for arranging data output by semicomductor testers to packet-based devices under test
12/06/2001	US20010049174 Method and system for configuring integrated systems on a chip
12/06/2001	US20010048634 Synchronous semiconductor memory device
12/06/2001	US20010048630 Semiconductor apparatus
12/06/2001	US20010048626 Virtual channel DRAM
12/06/2001	US20010048625 Dynamically configurated storage array with improved data access
12/06/2001	US20010048623 Semiconductor memory device having a circuit for fast operation
12/06/2001	US20010048621 Method for testing a multiplicity of word lines of a semiconductor memory configuration
12/06/2001	US20010048613 Dual-ported cams for a simultaneous operation flash memory
12/06/2001	US20010048610 Semiconductor memory device
12/06/2001	US20010048609 Nonvolatile semiconductor memory device having testing capabilities
12/06/2001	US20010048328 Semiconductor integrated circuit
12/06/2001	US20010048314 Component holder for testing devices and component holder system microlithography
12/06/2001	US20010047953 Enhanced grading and sorting of semiconductor devices using modular "plug-in" sort algorithms
12/05/2001	EP1160669A2 Integrated semiconductor memory with redundant cells
12/05/2001	EP1160668A2 Semiconductor integrated circuit and method of testing semiconductor integrated circuit
12/05/2001	EP1160580A1 Circuit for detecting a malfunction
12/05/2001	EP1159630A1 Distributed interface for parallel testing of multiple devices using a single tester channel
12/05/2001	EP0986786B1 Device for saving the configuration of a redundant system
12/05/2001	EP0699999B1 Memory architecture for automatic test equipment using vector module table
12/04/2001	US6327683 Device scan testing
12/04/2001	US6327682 Wafer burn-in design for DRAM and FeRAM devices
12/04/2001	US6327681 Data processor with built-in DRAM
12/04/2001	US6327680 Method and apparatus for array redundancy repair detection
12/04/2001	US6327224 On-chip method for measuring access time and data-pin spread
12/04/2001	US6327218 Integrated circuit time delay measurement apparatus
12/04/2001	US6327201 Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
12/04/2001	US6327200 Circuit and method for testing a memory device
12/04/2001	US6327199 Method for testing memory devices
12/04/2001	US6327198 Semiconductor memory device having a test mode setting circuit
12/04/2001	US6327197 Structure and method of a column redundancy memory
12/04/2001	US6327180 Semiconductor memory device for effecting erasing operation in block unit
11/2001
11/29/2001	WO2001091129A1 Dynamic configuration of storage arrays
11/29/2001	US20010047500 Semiconductor device testing apparatus
11/29/2001	US20010047496 Semiconductor test device for conducting an operation test in parallel on many chips in a wafer test and semiconductor test method
11/29/2001	US20010046175 Integrated circuit time delay measurement apparatus
11/29/2001	US20010046174 Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts
11/29/2001	US20010046166 Digital memory circuit
11/29/2001	US20010045841 Semiconductor integrated circuit, test method for the same, and recording device and communication equipment having the same
11/29/2001	US20010045581 Semiconductor device
11/29/2001	US20010045570 Semiconductor storage device having burn-in mode
11/29/2001	US20010045468 Ic card
11/29/2001	DE10124112A1 Semiconducting memory for high speed operation has word drive circuit driving word line in response to word reset signal, main word signal and word decoder signal
11/29/2001	DE10111030A1 Test pattern and strobe signal generator used in semiconductor test system, has delay insertion unit that inserts delay to time control data of specified event and duplicating unit for time control and event data
11/29/2001	DE10024875A1 Bauteilhalter für Testvorrichtungen und Bauteilhaltersystem Component holder for test equipment and component holder system
11/28/2001	EP1158536A2 Semiconductor memory device
11/28/2001	EP1158535A2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
11/28/2001	EP1158534A2 Semiconductor memory device
11/28/2001	EP1158533A1 Eeprom array with flash-like core

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