Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/2001
11/28/2001EP1158532A2 Semiconductor memory device
11/28/2001EP1158531A2 Semiconductor memory device
11/28/2001EP1158530A2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
11/28/2001EP1158526A2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
11/28/2001EP0966743B1 Method for testing an integrated circuit
11/28/2001EP0948793B1 High-speed test system for a memory device
11/28/2001EP0929901B1 Memory array, memory cell, and sense amplifier test and characterization
11/28/2001EP0929900B1 Data retention test for static memory cell
11/28/2001EP0929898B1 Memory block select using multiple word lines to address a single memory cell row
11/28/2001EP0929896B1 Memory including resistor bit-line loads
11/28/2001EP0929895B1 Active power supply filter
11/28/2001EP0729633B1 Sense amplifier for non-volatile semiconductor memory
11/28/2001EP0642137B1 Quiescent-current testable RAM
11/28/2001EP0590651B1 Dynamic random access memory device having power supply system appropriately biasing switching transistors and storage capacitors in burn-in testing process
11/28/2001CN1324078A Method of testing memory updating rate
11/28/2001CN1323989A Storage terminal calibration data based on affairs testing system for nonvolatile memory
11/27/2001US6324666 Memory test device and method capable of achieving fast memory test without increasing chip pin number
11/27/2001US6324657 On-clip testing circuit and method for improving testing of integrated circuits
11/27/2001US6324485 Application specific automated test equipment system for testing integrated circuit devices in a native environment
11/27/2001US6324120 Memory device having a variable data output length
11/27/2001US6324118 Synchronous semiconductor memory device having improved operational frequency margin at data input/output
11/27/2001US6324108 Application of external voltage during array VT testing
11/27/2001US6324107 Parallel test for asynchronous memory
11/27/2001US6324106 Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device
11/27/2001US6324105 Redundant row topology circuit, and memory device and test system using same
11/27/2001US6324104 Semiconductor integrated circuit device
11/27/2001US6324088 256 meg dynamic random access memory
11/27/2001US6323720 Internal voltage generator using anti-fuse
11/27/2001US6323671 Charge gain stress test circuit for nonvolatile memory and test method using the same
11/27/2001US6323664 Semiconductor memory device capable of accurately testing for defective memory cells at a wafer level
11/27/2001CA2186141C An iterative method of recording analog signals
11/22/2001WO2001088560A1 Arrangement for detecting malfunction
11/22/2001US20010044918 Semiconductor integrated circuit and design method and manufacturing method of the same
11/22/2001US20010044917 Memory data verify operation
11/22/2001US20010044916 Device and method for repairing a semiconductor memory
11/22/2001US20010043507 Synchronous semiconductor memory device capable of high speed reading and writing
11/22/2001US20010043502 Semiconductor memory device capable of efficient memory cell select operation with reduced element count
11/22/2001US20010043501 Redundancy circuitry for repairing defects in packaged memory having registers
11/22/2001US20010043500 Semiconductor device
11/22/2001US20010043498 Integrated memory and method for checking the operation of memory cells in an integrated memory
11/22/2001US20010043497 SRAM device
11/22/2001US20010043485 Integrated circuit with efficient testing arrangement
11/22/2001US20010043078 Test configuration for the functional testing of a semiconductor chip
11/22/2001DE10123582A1 Specimen pattern generator for semiconductor testing system of semiconductor memory components
11/22/2001DE10121459A1 Semiconductor device, such as fusible link semiconductor memory device, has fusible link circuit with its fusible link in series with an assessment transistor having a controlled impedance path
11/22/2001DE10121298A1 Flash memory testing process using data erasing and new data writing en block, or block per block
11/22/2001DE10113198A1 Adressdecoder und Verfahren für einen beschleunigten Belastungstest desselben The same address decoder and method for an accelerated stress test
11/21/2001EP0960422B1 Method for minimizing the access time for semiconductor memories
11/21/2001CN1323018A Card type recording medium and card recording medium reading out apparatus
11/20/2001US6321360 System including a ferroelectric memory
11/20/2001US6321358 Object reconstruction on object oriented data storage device
11/20/2001US6321356 Programmable pattern generator
11/20/2001US6321353 Intelligent binning for electrically repairable semiconductor chips
11/20/2001US6321320 Flexible and programmable BIST engine for on-chip memory array testing and characterization
11/20/2001US6321291 Method of measuring the speed of a memory unit in an integrated circuit
11/20/2001US6320812 Error catch RAM for memory tester has SDRAM memory sets configurable for size and speed
11/20/2001US6320805 Semiconductor device with external pins
11/20/2001US6320804 Integrated semiconductor memory with a memory unit a memory unit for storing addresses of defective memory cells
11/20/2001US6320803 Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits
11/20/2001US6320802 Program circuit suppressing stand-by current and permitting highly reliable operation, and semiconductor memory device using the program circuit
11/20/2001US6320801 Redundancy circuit and redundancy method for semiconductor memory device
11/20/2001US6320800 Semiconductor memory and nonvolatile semiconductor memory having redundant circuitry for replacing defective memory cell
11/20/2001US6320799 Semiconductor memory with a decoder circuit having a redundancy relief function
11/15/2001WO2001086660A1 Integrated circuit containing sram memory and method of testing same
11/15/2001WO2000062461A3 Interleavers and de-interleavers
11/15/2001US20010042233 Circuit and method for testing an integrated circuit
11/15/2001US20010042231 Memory testing apparatus and method
11/15/2001US20010042161 Semiconductor redundant memory provided in common
11/15/2001US20010041967 Semiconductor device testing apparatus and method for testing semiconductor device
11/15/2001US20010040836 Nonvolatile semiconductor memory and threshold voltage control method therefor
11/15/2001US20010040832 Method for checking a semiconductor memory device
11/15/2001US20010040830 Semiconductor memory device
11/15/2001US20010040829 Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester
11/15/2001DE10123154A1 Halbleitervorrichtungs-Prüfvorrichtung und Verfahren zum Prüfen einer Halbleitervorrichtung The semiconductor device testing apparatus and method for testing a semiconductor device
11/14/2001EP1154438A2 Programmable circuit with preview function
11/14/2001EP0961290B1 Flash memory with improved erasability and its circuitry
11/14/2001EP0928486B1 Device and method for testing integrated circuit dice in an integrated circuit module
11/14/2001EP0903752B1 Nonvolatile semiconductor memory
11/14/2001EP0586114B1 A semiconductor read only memory
11/14/2001CN1321892A Specific purpose semiconductor memory testing system based on event
11/13/2001US6317857 System and method for utilizing checksums to recover data
11/13/2001US6317852 Method to test auto-refresh and self refresh circuitry
11/13/2001US6317851 Memory test circuit and a semiconductor integrated circuit into which the memory test circuit is incorporated
11/13/2001US6317846 System and method for detecting faults in computer memories using a look up table
11/13/2001US6317373 Semiconductor memory device having a test mode and semiconductor testing method utilizing the same
11/13/2001US6317372 Semiconductor memory device equipped with serial/parallel conversion circuitry for testing memory cells
11/13/2001US6317371 Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory
11/13/2001US6317370 Timing fuse option for row repair
11/13/2001US6317368 Semiconductor integrated circuit device tested in batches
11/13/2001US6317366 Dynamic random access memory
11/13/2001US6317355 Nonvolatile ferroelectric memory device with column redundancy circuit and method for relieving failed address thereof
11/08/2001WO2001042803A3 Bit fail map compression with fail signature analysis
11/08/2001US20010039639 Error detection and correction circuit
11/08/2001US20010039634 Method of reducing test time for NVM cell-based FPGAs
11/08/2001US20010039602 Semiconductor memory device and method of controlling the same
11/08/2001US20010039601 Memory with large number of memory modules
11/08/2001US20010038569 Semiconductor integrated circuit device
11/08/2001US20010038559 Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
11/08/2001US20010038557 Circuit configuration for generating a reference voltage for reading a ferroelectric memory
11/08/2001US20010038554 Semiconductor memory device and restoration method therefor