| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 01/31/2002 | US20020012263 Semiconductor memory device |
| 01/31/2002 | US20020011894 256 Meg dynamic random access memory |
| 01/31/2002 | US20020011650 Semiconductor Device |
| 01/31/2002 | DE10040890C1 System for safe high temperature flash memory operation in vehicle involves programming memory before high temperature operation so that each record is stored redundantly |
| 01/31/2002 | DE10034897A1 Adresszähler zur Adressierung von synchronen hochfrequenten Digitalschaltungen, insbesondere Speicherbauelementen Address counter for addressing high-frequency synchronous digital circuits, in particular memory devices |
| 01/30/2002 | EP1176609A2 Testing of multilevel semiconductor memory |
| 01/30/2002 | EP1176608A2 Nonvolatile semiconductor storage device and test method therefor |
| 01/30/2002 | EP1176607A2 Method and device for testing signals setup and hold time in a circuit with synchronous data transfer |
| 01/30/2002 | EP1176606A2 Method and device for establishing and testing the response signal timing of a memory under test |
| 01/30/2002 | EP1176605A2 Integrated memory with magnetoresistive memory cells |
| 01/30/2002 | EP1176604A2 Method for testing a plurality of word lines in a semiconductor memory device |
| 01/30/2002 | EP1176511A2 Device for implementing redundancy in a memory module |
| 01/30/2002 | EP0858032B1 Circuit for repairing defective bit in semiconductor memory device and repairing method |
| 01/30/2002 | CN1078721C Data protection circuit |
| 01/30/2002 | CN1078719C Method for real-time measuirng memory chip divided into field in running of computer |
| 01/29/2002 | US6343366 BIST circuit for LSI memory |
| 01/29/2002 | US6343365 Large-scale integrated circuit and method for testing a board of same |
| 01/29/2002 | US6343048 Operation mode setting circuit of semiconductor memory device and method for setting thereof |
| 01/29/2002 | US6343038 Semiconductor memory device of shared sense amplifier system |
| 01/29/2002 | US6343037 Column redundancy circuit for semiconductor memory |
| 01/24/2002 | WO2002007167A2 Method for selecting an optimal level of redundancy in the design of memories |
| 01/24/2002 | WO2002006960A1 Memory access method and apparatus |
| 01/24/2002 | US20020010891 Redundant memory access system |
| 01/24/2002 | US20020010890 Semiconductor integrated circuit and method of testing semiconductor integrated circuit |
| 01/24/2002 | US20020010884 Test method for switching to redundant circuit in SRAM pellet |
| 01/24/2002 | US20020010878 Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits |
| 01/24/2002 | US20020010877 System for testing fast integrated digital circuits, in particular semiconductor memory modules |
| 01/24/2002 | US20020010876 Method for operating memory devices for storing data |
| 01/24/2002 | US20020010559 Semiconductor device having a mode of functional test |
| 01/24/2002 | US20020009007 Method and device for generating digital signal patterns |
| 01/24/2002 | US20020009006 Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device |
| 01/24/2002 | US20020009004 Semiconductor memory device enabling test of timing standard for strobe signal and data signal with ease, and subsidiary device and testing device thereof |
| 01/24/2002 | US20020009003 Integrated semiconductor memory having memory cells in a plurality of memory cell arrays and method for repairing such a memory |
| 01/24/2002 | US20020008998 Repair analysis circuit for redundancy, redundant repairing method, and semiconductor device |
| 01/24/2002 | US20020008991 Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell |
| 01/24/2002 | US20020008984 256 Meg dynamic random access memory |
| 01/24/2002 | US20020008555 Semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other |
| 01/24/2002 | US20020008509 Semiconductor memory integrated circuit operating at different test modes |
| 01/24/2002 | US20020008503 Method and device for testing set-up time and hold time of signals of a circuit with clocked data transfer |
| 01/24/2002 | US20020008235 Integrated circuit with test mode, and test configuration for testing an integrated circuit |
| 01/24/2002 | US20020007923 Fabric light control window covering |
| 01/24/2002 | DE10110934A1 Integrierte Halbleiterschaltung, Speicherreparaturverfahren für eine integrierte Halbleiterschaltung und Computererzeugnis A semiconductor integrated circuit memory repair method for a semiconductor integrated circuit and computer product |
| 01/24/2002 | DE10034062A1 Integrierter Halbleiterspeicher mit Speicherzellen in mehre-ren Speicherzellenfeldern und Verfahren zur Reparatur eines solchen Speichers Integrated semiconductor memory having memory cells in several-ren memory cell arrays and methods for repair of such a memory |
| 01/24/2002 | DE10032274A1 Magnetoresistive random access memory controls sense amplifier such that column lines not connected to selected memory cells, are electrically isolated in sense amplifier for selectively reading and writing data signal |
| 01/24/2002 | DE10031947A1 Schaltungsanordnung zum Ausgleich unterschiedlicher Spannungen auf Leitungszügen in integrierten Halbleiterschaltungen Circuitry to compensate for different voltages on line trains in semiconductor integrated circuits |
| 01/23/2002 | EP1174884A2 Address counter for addressing synchronous high frequency digital circuits, in particular memory elements |
| 01/23/2002 | EP1173853A1 Failure capture apparatus and method for automatic test equipment |
| 01/23/2002 | EP0935802B1 Staggered row line firing in a single ras cycle |
| 01/23/2002 | CN1332869A Leveizing transfer delays for channel of memory devices in memory subsystem |
| 01/23/2002 | CN1332459A Semiconductor integrated circuit and its storage repairing method |
| 01/22/2002 | US6341094 Method and apparatus for functional testing of memory related circuits |
| 01/22/2002 | US6341093 SOI array sense and write margin qualification |
| 01/22/2002 | US6341092 Designing memory for testability to support scan capability in an asic design |
| 01/22/2002 | US6341091 Method and system for testing a bit cell in a memory array |
| 01/22/2002 | US6341090 Method for repairing semiconductor integrated circuit device |
| 01/22/2002 | US6341089 Semiconductor memory device allowing effective detection of leak failure |
| 01/22/2002 | US6341085 Storage device employing a flash memory |
| 01/17/2002 | WO2002005288A1 A method for performing write and read operations in a passive matrix memory, and apparatus for performing the method |
| 01/17/2002 | WO2002005093A1 Method and circuit for accelerating redundant address matching |
| 01/17/2002 | US20020007480 Circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits |
| 01/17/2002 | US20020006073 Decoding circuit for controlling activation of wordlines in a semiconductor memory device |
| 01/17/2002 | US20020006067 Integrated circuit memory devices having efficient multi-row address test capability and methods of operating same |
| 01/17/2002 | US20020006066 Testable nonvolatile semiconductor device |
| 01/17/2002 | US20020006065 Apparatus for analyzing failure for semiconductor memory device |
| 01/17/2002 | US20020006064 Semiconductor memory device and method of checking same for defect |
| 01/17/2002 | US20020006062 Semiconductor device |
| 01/17/2002 | US20020006061 Integrated memory having memory cells with a magnetoresistive storage property |
| 01/17/2002 | US20020005737 256 Meg dynamic random access memory |
| 01/17/2002 | US20020005729 Method and system for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus |
| 01/17/2002 | DE10112311A1 Verfahren und Einrichtung zum Kalibrieren zur Korrektur von Impulsbreitenzeitfehlern beim Testen integrierter Schaltungen Method and device for calibrating to correct for pulse width time errors in the testing of integrated circuits |
| 01/17/2002 | DE10031946A1 Digital integrated circuit with built-in timing delay circuit for e.g. autorefresh DRAM, has regulatable current source in timing circuit to produce output signal with a delay with respect to reference timing |
| 01/17/2002 | DE10030234A1 Integrierter Speicher mit Speicherzellen mit magnetoresistivem Speichereffekt Integrated memory having memory cells with a magnetoresistive memory effect |
| 01/16/2002 | EP1172855A2 Integrated semiconductor memory with memory cells in a plurality of memory cell arrays and method of repairing said memory |
| 01/16/2002 | EP1172821A1 Semiconductor storage device and method for evaluating the same |
| 01/16/2002 | EP1025564B1 Programmable logic device memory cell circuit |
| 01/16/2002 | EP0738418B1 A method of testing a memory address decoder |
| 01/16/2002 | CN1331819A IC memory having redundancy |
| 01/16/2002 | CN1331818A Clumn redundancy circuit with reduced signal path delay |
| 01/16/2002 | CN1331805A Lead frame structure for testing integrated circuits |
| 01/16/2002 | CN1331471A Circuit device for compensating different voltage on connection wire of integrated semiconductor circuit |
| 01/15/2002 | US6339557 Charge retention lifetime evaluation method for nonvolatile semiconductor memory |
| 01/15/2002 | US6339555 Semiconductor memory device enabling test of timing standard for strobe signal and data signal with ease, and subsidiary device and testing device thereof |
| 01/15/2002 | US6339554 Semiconductor memory device with replacement programming circuit |
| 01/15/2002 | US6339539 Content addressable memory having read/write capabilities that do not interrupt continuous search cycles |
| 01/15/2002 | US6339357 Semiconductor integrated circuit device capable of externally monitoring internal voltage |
| 01/15/2002 | US6339228 DRAM cell buried strap leakage measurement structure and method |
| 01/10/2002 | WO2002003450A2 Automated determination and display of the physical location of a failed cell in an array of memory cells |
| 01/10/2002 | US20020004923 Integrated circuit |
| 01/10/2002 | US20020004921 Method of deciding error rate and semiconductor integrated circuit device |
| 01/10/2002 | US20020004867 Memory device which receives an external reference voltage signal |
| 01/10/2002 | US20020003747 Semiconductor memory device |
| 01/10/2002 | US20020003744 Programmable low voltage decode circuits with ultra-thin tunnel oxides |
| 01/10/2002 | US20020003742 Line segmentation in programmable logic devices having redundancy circuitry |
| 01/10/2002 | US20020003733 SOI array sense and write margin qualification |
| 01/10/2002 | US20020003732 Semiconductor memory device allowing spare memory cell to be tested efficiently |
| 01/10/2002 | US20020003731 Memory testing method |
| 01/10/2002 | US20020003730 Semiconductor memory device allowing switching of word configuration |
| 01/10/2002 | US20020003729 Semiconductor storage device and method for evaluating the same |
| 01/10/2002 | US20020003728 Integrated memory with redundancy and method for repairing an integrated memory |
| 01/10/2002 | US20020003727 Integrated memory having memory cells with magnetoresistive memory effect |