| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 05/16/2002 | DE10153753A1 Memory tester for forbidding programming of addresses in bad columns, includes automatic data replacement mechanism |
| 05/16/2002 | DE10153665A1 Memory tester for enhanced re-decoding, involves applying mask on data result without previous storage of test result |
| 05/16/2002 | DE10055096A1 Memory management of semiconductor type memory in which the advantages or ROM, i.e. high speed access, are combined with the flexibility of RAM where necessary |
| 05/16/2002 | CA2426040A1 At-speed built-in self testing of multi-port compact srams |
| 05/15/2002 | EP1205938A2 Integrated circuit with test mode and method for testing a plurality of such circuits |
| 05/15/2002 | EP0764330B1 Eeprom array with flash-like core |
| 05/15/2002 | CN1349259A Fuse circuit used for semiconductor integrated circuit |
| 05/15/2002 | CN1084878C Assembly and method for testing integrated circuit device |
| 05/14/2002 | US6389575 Data integrity checking apparatus |
| 05/14/2002 | US6389564 DRAM circuit having a testing unit and its testing method |
| 05/14/2002 | US6389563 Semiconductor memory test circuit and method for the same |
| 05/14/2002 | US6389525 Pattern generator for a packet-based memory tester |
| 05/14/2002 | US6388946 Circuit and method for incrementally selecting word lines |
| 05/14/2002 | US6388941 Semiconductor device |
| 05/14/2002 | US6388930 Method and apparatus for ram built-in self test (BIST) address generation using bit-wise masking of counters |
| 05/14/2002 | US6388929 Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same |
| 05/14/2002 | US6388928 Method and system for reduction of test time for analog chip manufacturing |
| 05/14/2002 | US6388927 Direct bit line-bit line defect detection test mode for SRAM |
| 05/14/2002 | US6388925 Row redundancy scheme capable of replacing defective wordlines in one block with redundant wordlines in another block |
| 05/14/2002 | US6388920 Semiconductor memory device having faulty cells |
| 05/14/2002 | US6388919 Memory controller for flash memory system and method for writing data to flash memory device |
| 05/14/2002 | US6388853 Method and apparatus providing final test and trimming for a power supply controller |
| 05/14/2002 | US6388460 Alternate timing wafer burn-in method |
| 05/10/2002 | WO2002037504A1 Memory defect remedy analyzing method and memory test instrument |
| 05/10/2002 | WO2002037503A1 Semiconductor memory, method of testing semiconductor memory, and method of manufacturing semiconductor memory |
| 05/10/2002 | WO2002037130A2 Method for testing integrated circuits |
| 05/10/2002 | WO2001097226A3 Semiconductor memory having segmented row repair |
| 05/09/2002 | US20020056063 Power saving feature during memory self-test |
| 05/09/2002 | US20020056062 Circuit and method for testing a data memory |
| 05/09/2002 | US20020056061 Circuit for reducing test time and semiconductor memory device including the circuit |
| 05/09/2002 | US20020056057 Local heating of memory modules tested on a multi-motherboard tester |
| 05/09/2002 | US20020056056 Electronic control apparatus with memory validation and method |
| 05/09/2002 | US20020054532 Semiconductor memory device having function of supplying stable power supply voltage |
| 05/09/2002 | US20020054529 Semiconductor integrated circuit device having efficiently arranged link program circuitry |
| 05/09/2002 | US20020054528 Semiconductor memory testing method and apparatus |
| 05/09/2002 | US20020054526 Semiconductor memory and its test method |
| 05/09/2002 | US20020054525 Semiconductor memory device having a relaxed pitch for sense amplifiers |
| 05/09/2002 | US20020054524 Redundant encoding for buried metal fuses |
| 05/09/2002 | US20020054521 Semiconductor device making reliable initial setting |
| 05/09/2002 | US20020054518 Semiconductor memory device having redundancy |
| 05/09/2002 | US20020054507 Nonvolatile semiconductor memory device |
| 05/09/2002 | US20020053943 Semiconductor integrated circuit device capable of externally monitoring internal voltage |
| 05/09/2002 | US20020053694 Method of forming a memory cell with self-aligned contacts |
| 05/08/2002 | EP1204122A2 A method of determining the location of a defect in an integrated circuit and how to use this integrated circuit |
| 05/08/2002 | EP0935256B1 Test method for writable nonvolatile semiconductor memory device |
| 05/08/2002 | EP0804762B1 Self-diagnostic asynchronous data buffers |
| 05/08/2002 | EP0712079B1 Recovery method for a high availability data processing system |
| 05/08/2002 | DE10052292A1 Electronic data storage method for semiconductor memory with data memory and electrically-erasable and programmable array-logic coupled to host computer |
| 05/08/2002 | DE10052211A1 Test arrangement for integrated circuit memory chips |
| 05/07/2002 | US6385747 Testing of replicated components of electronic device |
| 05/07/2002 | US6385746 Memory test circuit |
| 05/07/2002 | US6385129 Delay locked loop monitor test mode |
| 05/07/2002 | US6385125 Synchronous semiconductor integrated circuit device capable of test time reduction |
| 05/07/2002 | US6385104 Semiconductor memory device having a test mode decision circuit |
| 05/07/2002 | US6385103 Semiconductor memory device having a circuit for testing memories |
| 05/07/2002 | US6385102 Redundancy multiplexer for a semiconductor memory configuration |
| 05/07/2002 | US6385100 Semiconductor memory device with improved column selecting operation |
| 05/07/2002 | US6385098 Method and apparatus for supplying regulated power to memory device components |
| 05/07/2002 | US6385084 Semiconductor memory |
| 05/07/2002 | US6385081 Semiconductor integrated circuit |
| 05/07/2002 | US6385071 Redundant scheme for CAMRAM memory array |
| 05/07/2002 | US6384665 Method and circuitry for soft fuse row redundancy with simple fuse programming |
| 05/07/2002 | US6384664 Differential voltage sense circuit to detect the state of a CMOS process compatible fuses at low power supply voltages |
| 05/02/2002 | WO2002008904A3 System initialization of microcode-based memory built-in self-test |
| 05/02/2002 | WO2001093034A3 Dual-ported cams for a simultaneous operation flash memory |
| 05/02/2002 | US20020053051 Digital signal forming method, disc recording media using the same, and reproducing method thereof |
| 05/02/2002 | US20020053048 Semiconductor integrated circuit device |
| 05/02/2002 | US20020053042 On chip error correction for devices in a solid state drive |
| 05/02/2002 | US20020052070 Apparatus of repairing memory cell and method therefor |
| 05/02/2002 | US20020051404 Synchronous semiconductor integrated circuit device capable of test time reduction |
| 05/02/2002 | US20020051400 Semiconductor integrated circuit device and method of manufacturing thereof |
| 05/02/2002 | US20020051399 Semiconductor device including a fuse circuit in which the electric current is cut off after blowing so as to prevent voltage fall |
| 05/02/2002 | US20020051396 Synchronous semiconductor memory device and refresh method thereof |
| 05/02/2002 | US20020051394 Flash memory control method and apparatus processing system therewith |
| 05/02/2002 | US20020051392 Semiconductor memory device |
| 05/02/2002 | US20020051385 Fail number detecting circuit of flash memory |
| 05/02/2002 | US20020050840 Circuit configuration and method for accelerating aging in an MRAM |
| 05/02/2002 | EP1200963A1 Testing rambus memories |
| 05/02/2002 | DE10062093A1 Electronic circuit suppresses access to memory for faulty address test of storage range in memory field |
| 04/30/2002 | US6381725 Disk device and data error correction method thereof |
| 04/30/2002 | US6381718 Current controlled multi-state parallel test for semiconductor device |
| 04/30/2002 | US6381715 System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module |
| 04/30/2002 | US6381708 Method for decoding addresses for a defective memory array |
| 04/30/2002 | US6381707 System for decoding addresses for a defective memory array |
| 04/30/2002 | US6381550 Method of utilizing fast chip erase to screen endurance rejects |
| 04/30/2002 | US6381195 Circuit, apparatus and method for generating address |
| 04/30/2002 | US6381192 Address buffer in a flash memory |
| 04/30/2002 | US6381186 Dynamic random access memory |
| 04/30/2002 | US6381185 Method and a circuit architecture for testing an integrated circuit comprising a programmable, non-volatile memory |
| 04/30/2002 | US6381184 Method and apparatus for rapidly testing memory devices |
| 04/30/2002 | US6381183 Column redundancy for prefetch |
| 04/30/2002 | US6381174 Non-volatile memory device with redundant columns |
| 04/30/2002 | US6381167 Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof |
| 04/30/2002 | US6380782 Integrated circuit |
| 04/25/2002 | WO2002033708A1 Memory defect redress analysis treating method, and memory testing apparatus performing the method |
| 04/25/2002 | WO2002033549A1 Method for operating a processor-controlled system |
| 04/25/2002 | WO2001067601A3 Test circuit configuration and method for testing a large number of transistors |
| 04/25/2002 | US20020049951 Error correction chip for memory applications |
| 04/25/2002 | US20020049946 Synchronous semiconductor memory device capable of performing operation test at high speed while reducing burden on tester |
| 04/25/2002 | US20020049943 Semiconductor test system |