| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 06/27/2002 | US20020080004 Fuse circuit using capacitors as fuse elements |
| 06/27/2002 | US20020079916 Method for testing an integrated circuit |
| 06/27/2002 | US20020079913 Module test socket for test adapters |
| 06/27/2002 | US20020079252 Enhanced grading and sorting of semiconductor devices using modular "plug-in" sort algorithms |
| 06/27/2002 | DE10135559A1 Statische Halbleiterspeichervorrichtung mit einem Redundanzsystem The static semiconductor memory device having a redundancy system |
| 06/27/2002 | DE10062404A1 Faulty memory cell address reduction method compares each detected faulty memory cell address with second fault address for word and/or bit line to be repaired for eliminating duplications |
| 06/27/2002 | DE10061243A1 Data propagation time determination method for databus in semiconductor memory has time interval between transfer of data to output buffer and transfer to output altered in dependence on data comparison |
| 06/26/2002 | EP1217630A2 Test method for integrated circuit |
| 06/26/2002 | EP1217628A1 Method and system to adjust an internal temporisation or any other characteristic in an integrated circuit and integrated circuit thereof |
| 06/26/2002 | EP1217524A2 Method and system for data block sparing in a solid-state storage device |
| 06/26/2002 | EP1216477A1 Circuit and method for column redundancy for high bandwidth memories |
| 06/26/2002 | CN1355889A Method and apparatus for testing video display chip |
| 06/26/2002 | CN1355536A Semiconductor memory device with multiple low-pissipation module type |
| 06/26/2002 | CN1086836C Semiconductor device and unit for driving same |
| 06/25/2002 | US6412089 Background read scanning with defect reallocation |
| 06/25/2002 | US6412088 Method and apparatus for using block reread |
| 06/25/2002 | US6412051 System and method for controlling a memory array in an information handling system |
| 06/25/2002 | US6412036 Apparatus for testing input/output interface of computer system |
| 06/25/2002 | US6411563 Semiconductor integrated circuit device provided with a logic circuit and a memory circuit and being capable of efficient interface between the same |
| 06/25/2002 | US6411556 Semiconductor memory device with improved layout and redundancy determining circuits |
| 06/25/2002 | US6410936 Semiconductor device |
| 06/25/2002 | US6410350 Detecting die speed variations |
| 06/20/2002 | WO2001059571A3 Command-driven test modes |
| 06/20/2002 | US20020078408 Apparatus for testing computer memory |
| 06/20/2002 | US20020078407 Memory interlace-checking method |
| 06/20/2002 | US20020075749 Method and apparatus for generating memory addresses for testing memory devices |
| 06/20/2002 | US20020075743 Antifuse address detecting circuit programmable by applying a high voltage and semiconductor integrated circuit device provided with the same |
| 06/20/2002 | US20020075740 System for measuring access time of embedded memories |
| 06/20/2002 | US20020075733 Redundant circuit for memory device |
| 06/20/2002 | US20020075730 Method and apparatus for testing high-speed circuits based on slow-speed signals |
| 06/20/2002 | US20020075721 Semiconductor integrated circuit with memory redundancy circuit |
| 06/20/2002 | US20020075067 Semiconductor integrated circuit |
| 06/20/2002 | US20020075062 Semiconductor device capable of adjusting an internal power supply potential in a wide range |
| 06/20/2002 | US20020074666 Semiconductor device having identification number, manufacturing method thereof and electronic device |
| 06/20/2002 | DE10062123C1 Reference current source for memory cell read-out uses sub-groups of parallel transistors connected to common switches coupled together on their output side |
| 06/20/2002 | DE10056883C1 Defective memory cell replacement method for semiconductor memory has further memory region used for replacing memory region containing memory cell identified as defective |
| 06/19/2002 | EP1215682A2 Initializing an integrated circuit using compressed data from a remote fusebox |
| 06/19/2002 | EP1214713A1 Architecture, method(s) and circuitry for low power memories |
| 06/19/2002 | EP0858033B1 Circuit for repairing defective bit in semiconductor memory device and repairing method |
| 06/19/2002 | EP0856793B1 Circuit for repairing defective bit in semiconductor memory device and repairing method |
| 06/18/2002 | US6408412 Method and structure for testing embedded analog/mixed-signal cores in system-on-a-chip |
| 06/18/2002 | US6408411 Two pass multi-state parallel test for semiconductor device |
| 06/18/2002 | US6408401 Embedded RAM with self-test and self-repair with spare rows and columns |
| 06/18/2002 | US6407955 Integrated circuit having an on-board reference generator |
| 06/18/2002 | US6407954 Nonvolatile semiconductor memory device |
| 06/18/2002 | US6407953 Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays |
| 06/18/2002 | US6407952 Semiconductor memory |
| 06/18/2002 | US6407950 Semiconductor memory device capable of implementing redundancy-based repair efficiently in relation to layout and operating speed and semiconductor integrated circuit device having such semiconductor memory device |
| 06/13/2002 | WO2002047091A1 Memory circuit test system, semiconductor device, and method of tesing memory |
| 06/13/2002 | WO2002046929A1 Method of controlling flash memory |
| 06/13/2002 | US20020073373 Test method of semiconductor intergrated circuit and test pattern generator |
| 06/13/2002 | US20020073368 Pre-stored digital word generator |
| 06/13/2002 | US20020073367 Method and integrated circuit for testing a memory having a number of memory banks |
| 06/13/2002 | US20020073366 Semiconductor device test method for optimizing test time |
| 06/13/2002 | US20020073363 Data processing system |
| 06/13/2002 | US20020071334 Testing of high speed DDR interface using single clock edge triggered tester data |
| 06/13/2002 | US20020071326 Apparatus for analyzing failure for semiconductor memory device |
| 06/13/2002 | US20020071325 Built-in self-test arrangement for integrated circuit memory devices |
| 06/13/2002 | US20020071324 Semiconductor memory |
| 06/13/2002 | US20020070748 System for testing fast synchronous digital circuits, particularly semiconductor memory chips |
| 06/13/2002 | US20020070746 Method and apparatus for testing semiconductor devices |
| 06/13/2002 | DE10144660A1 Managing inversion characteristics in memory tester involves storing inversion mask in memory, selectively inverting data using mask, applying masked output signal to data channels |
| 06/13/2002 | DE10139819A1 Verfahren zum Betrieb von Speicherseiten eines DRAM und entsprechende DRAM-Systemstruktur Method for the operation of a DRAM memory pages and corresponding DRAM system structure |
| 06/13/2002 | DE10060438A1 Testing device for parallel testing of IC's, has active bus module inserted in signal path between test system and tested IC |
| 06/13/2002 | DE10060437A1 Needle card device for parallel testing of IC's has active module inserted in signal path between test system and each tested IC |
| 06/13/2002 | DE10058969A1 Cell field for semiconducting memory has at least one data line to which dummy memory cells are connected to write dummy memory cells via dummy data line |
| 06/13/2002 | DE10058779A1 Vorrichtung zum Stressen einer integrierten ferroelektrischen Halbleiterspeicherschaltung A device for stressing an integrated ferroelectric semiconductor memory circuit |
| 06/13/2002 | DE10049441A1 Verfahren zum Betrieb eines von einem Prozessor gesteuerten Systems Method for operating a system controlled by a processor |
| 06/12/2002 | EP1212628A1 Variable length pattern generator for chip tester system |
| 06/12/2002 | EP1040420B1 Process for repairing integrated circuits |
| 06/12/2002 | EP0910826B1 Block erasable memory system defect handling |
| 06/12/2002 | CN1353423A Self-test method of memory |
| 06/11/2002 | US6405332 Storage device and alternate processing method for defective sectors of the same |
| 06/11/2002 | US6405331 Method for performing a built-in self-test procedure on embedded memory device |
| 06/11/2002 | US6405323 Defect management for interface to electrically-erasable programmable read-only memory |
| 06/11/2002 | US6405150 Program storage device containing instructions that are spaced apart by unused bits that end on word boundaries and which generate chip testing bit streams of any length |
| 06/11/2002 | US6404698 Semiconductor memory device having column redundancy function |
| 06/11/2002 | US6404684 Test interface circuit and semiconductor integrated circuit device including the same |
| 06/11/2002 | US6404683 Nonvolatile semiconductor memory device and test method with memory-assisted roll call |
| 06/11/2002 | US6404680 Circuit to check overerasing of repair fuse cells |
| 06/11/2002 | US6404663 Semiconductor integrated circuit having testing mode for modifying operation timing |
| 06/11/2002 | US6404264 Fuse latch having multiplexers with reduced sizes and lower power consumption |
| 06/11/2002 | US6404250 On-chip circuits for high speed memory testing with a slow memory tester |
| 06/06/2002 | WO2002045094A2 Method and apparatus for built-in self-repair of memory storage arrays |
| 06/06/2002 | WO2002045093A1 Semiconductor memory device and address conversion circuit |
| 06/06/2002 | WO2002045092A1 Fail analysis device |
| 06/06/2002 | US20020069398 Correcting method of mask and mask manufactured by said method |
| 06/06/2002 | US20020069383 Method for testing a memory array |
| 06/06/2002 | US20020069382 Semiconductor integrated circuit device and method of testing it |
| 06/06/2002 | US20020069381 Nonvolatile semiconductor memory device with a fail bit detecting scheme and method for counting the number of fail bits |
| 06/06/2002 | US20020069026 Semiconductor device capable of test mode operation |
| 06/06/2002 | US20020067647 Semiconductor integrated circuit device |
| 06/06/2002 | US20020067646 Method and apparatus for generating memory addresses for testing memory devices |
| 06/06/2002 | US20020067645 Method and system for increasing timing margins without deteriorating a data transfer rate |
| 06/06/2002 | US20020067644 Wordline driver for ensuring equal stress to wordlines in multi row address disturb test and method of driving the wordline driver |
| 06/06/2002 | US20020067633 Semiconductor integrated circuit |
| 06/06/2002 | DE10129263A1 Non-volatile ferroelectric memory has pulse width generating unit for varying width of reproduction pulse and outputting varied width to word line driver to identify defective cell |
| 06/06/2002 | DE10103991C1 Temperature detection method for semiconductor component uses evaluation of replacement voltage of memory cell transistor |
| 06/05/2002 | EP1097460B1 Integrated circuit comprising a self-test device for executing a self-test of the integrated circuit |
| 06/05/2002 | EP1062573B1 State copying method for software update |