| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 07/16/2002 | US6421278 Method of improving an electrostatic discharge characteristic in a flash memory device |
| 07/16/2002 | US6420921 Delay signal generating apparatus and semiconductor test apparatus |
| 07/16/2002 | US6420896 Semiconductor integrated circuit |
| 07/11/2002 | WO2002054411A2 Method for reading semiconductor die information in a parallel test and burn-in system |
| 07/11/2002 | WO2002025957A3 Memory module and memory component built-in self test |
| 07/11/2002 | WO2002014886A3 Method to descramble the data mapping in memory circuits |
| 07/11/2002 | WO2001015174A9 A memory module test system with reduced driver output impedance |
| 07/11/2002 | US20020091890 Synchronous memory device having automatic precharge |
| 07/11/2002 | US20020090747 Method for examining structures on a wafer |
| 07/11/2002 | US20020089887 Built-in self-test arrangement for integrated circuit memory devices |
| 07/11/2002 | US20020089881 High speed semiconductor memory device with short word line switching time |
| 07/11/2002 | US20020089879 Semiconductor memory device of low power consumption |
| 07/11/2002 | US20020089341 Test configuration and test method for testing a plurality of integrated circuits in parallel |
| 07/11/2002 | DE10162193A1 Semiconductor memory device for processing internal command signals, addresses and data input/output uses an internal timing signal inverted by an external timing signal, logical combination circuits and clock pulse generators. |
| 07/11/2002 | DE10062094A1 Integrated circuit for adapting to adjustments has an electrical fuse, a memory element and a test circuit for reading out data stored in the electrical fuse and the memory element. |
| 07/11/2002 | DE10062092A1 Electronic circuit for testing a memory cell in a main memory area has a comparator, an error location store, a data output and a switch controlled by a reader-mode control signal. |
| 07/10/2002 | EP1221699A2 Fuse circuit using capacitors as fuse elements |
| 07/10/2002 | EP1221165A1 Circuit and method for a multiplexed redundancy scheme in a memory device |
| 07/10/2002 | EP1033029B1 Affine transformation means and method of affine transformation |
| 07/10/2002 | EP1012848B1 System for storing information with data compression |
| 07/10/2002 | CN1357893A Method and device of using compressed data in far-end fuse box to initialize integrated circuit |
| 07/10/2002 | CN1087473C Semiconductor memory device having cache function |
| 07/10/2002 | CN1087435C Active matrix panel and method for fabricating the same |
| 07/09/2002 | US6418072 Semiconductor integrated circuit |
| 07/09/2002 | US6418071 Method of testing a memory cell |
| 07/09/2002 | US6418070 Memory device tester and method for testing reduced power states |
| 07/09/2002 | US6418069 Method of repairing defective memory cells of an integrated memory |
| 07/09/2002 | US6418068 Self-healing memory |
| 07/09/2002 | US6418067 Semiconductor memory device suitable for merging with logic |
| 07/09/2002 | US6418066 Semiconductor memory device having multibit data bus and redundant circuit configuration with reduced chip area |
| 07/09/2002 | US6418057 Nonvolatile semiconductor memory device capable of correctly performing erasure/programming completion determination even in presence of defective bit |
| 07/09/2002 | US6418051 Non-volatile memory device with configurable row redundancy |
| 07/09/2002 | US6418044 Method and circuit for determining sense amplifier sensitivity |
| 07/09/2002 | US6417726 Semiconductor device capable of adjusting an internal power supply potential in a wide range |
| 07/09/2002 | US6417695 Antifuse reroute of dies |
| 07/04/2002 | WO2002052619A1 Memory access and data control |
| 07/04/2002 | WO2002052576A1 Enhanced special programming mode |
| 07/04/2002 | WO2002052575A1 Special programming mode with external verification |
| 07/04/2002 | US20020087927 Method for testing integrated circuits |
| 07/04/2002 | US20020087926 Device and method for reducing the number of addresses of faulty memory cells |
| 07/04/2002 | US20020087777 Synchronous integrated circuit device |
| 07/04/2002 | US20020086449 Semiconducter memory device with redundancy |
| 07/04/2002 | US20020085445 Semiconductor memory device enabling reduction of test time period |
| 07/04/2002 | US20020085443 Apparatus for selecting bank in semiconductor memory device |
| 07/04/2002 | US20020085439 Method for reading semiconductor die information in a parallel test and burn-in system |
| 07/04/2002 | US20020085432 Recovery of useful areas of partially defective synchronous memory components |
| 07/04/2002 | US20020085431 Redundancy circuit of semiconductor memory device |
| 07/04/2002 | US20020085429 Semiconductor memory device capable of outputting a wordline voltage via an external pin |
| 07/04/2002 | US20020085426 Apparatus for varying data input/output path in semiconductor memory device |
| 07/04/2002 | US20020085425 Differential signal path for high speed data transmission in flash memory |
| 07/04/2002 | US20020085416 Storage device employing a flash memory |
| 07/04/2002 | US20020085415 Differential redundancy multiplexor for flash memory devices |
| 07/04/2002 | US20020085414 Programmable read-only memory and method for operating the read-only memory |
| 07/04/2002 | US20020085406 Circuit and method for testing a ferroelectric memory device |
| 07/04/2002 | DE10064478A1 Verfahren zur Prüfung einer integrierten Schaltung A method for testing an integrated circuit |
| 07/04/2002 | DE10034899C1 System zum Test schneller synchroner Halbleiterschaltungen A system for testing high-speed synchronous semiconductor circuits |
| 07/03/2002 | EP1220231A2 Circuit and method for performing a stress test on a ferroelectric memory device |
| 07/03/2002 | EP1220230A2 Circuit and method for testing a ferroelectric memory device |
| 07/03/2002 | EP1218887A1 Method and apparatus for supplying regulated power to memory device components |
| 07/03/2002 | EP1218821A1 Improved memory integrity for meters |
| 07/03/2002 | EP1099224B1 Circuit for generating a reference voltage for reading out from a ferroelectric memory |
| 07/03/2002 | EP0772202B1 Memory device with reduced number of fuses |
| 07/03/2002 | EP0733973B1 Information coherency detector contained in an integrated circuit |
| 07/02/2002 | US6415408 Multi-stage algorithmic pattern generator for testing IC chips |
| 07/02/2002 | US6415406 Integrated circuit having a self-test device and method for producing the integrated circuit |
| 07/02/2002 | US6415403 Programmable built in self test for embedded DRAM |
| 07/02/2002 | US6415399 Semiconductor memory device requiring performance of plurality of tests for each of plurality of memory circuits and method for testing the same |
| 07/02/2002 | US6415397 Automated multi-PC-motherboard memory-module test system with robotic handler and in-transit visual inspection |
| 07/02/2002 | US6415339 Memory device having a plurality of programmable internal registers and a delay time register |
| 07/02/2002 | US6415205 Occupancy sensor and method of operating same |
| 07/02/2002 | US6414901 Circuit for generating address of semiconductor memory device |
| 07/02/2002 | US6414896 Semiconductor memory device having column redundancy scheme to improve redundancy efficiency |
| 07/02/2002 | US6414890 Semiconductor memory device capable of reliably performing burn-in test at wafer level |
| 07/02/2002 | US6414889 Method and apparatus thereof for burn-in testing of a static random access memory |
| 07/02/2002 | US6414888 Semiconductor storage device having burn-in mode |
| 07/02/2002 | US6414887 Semiconductor memory device |
| 07/02/2002 | US6414886 Integrated memory with interblock redundancy |
| 07/02/2002 | US6414885 Semiconductor integrated circuit and integrated circuit system |
| 07/02/2002 | US6414876 Flash EEprom system |
| 07/02/2002 | US6414874 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 07/02/2002 | US6414368 Microcomputer with high density RAM on single chip |
| 06/27/2002 | WO2002050840A2 Data processing device with a write once memory (wom) |
| 06/27/2002 | WO2002007167A3 Method for selecting an optimal level of redundancy in the design of memories |
| 06/27/2002 | US20020083385 Special programming mode with hashing |
| 06/27/2002 | US20020083384 System for optimizing anti-fuse repair time using fuse ID |
| 06/27/2002 | US20020083383 Method for testing memories with seamless data input/output by interleaving seamless bank commands |
| 06/27/2002 | US20020083381 Special programming mode with external verification |
| 06/27/2002 | US20020083380 Integrated circuit having a data processing unit and a buffer memory |
| 06/27/2002 | US20020083369 Multi-staged bios-based memory testing |
| 06/27/2002 | US20020083363 Memory access and data control |
| 06/27/2002 | US20020083291 Nonvolatile semiconductor memory |
| 06/27/2002 | US20020082791 Method and system for the adjustment of an internal timing signal or a corresponding reference in an integrated circuit, and corresponding integrated circuit |
| 06/27/2002 | US20020080668 Current controlled multi-state parallel test for semiconductor device |
| 06/27/2002 | US20020080667 Semiconductor integrated circuit having test circuit |
| 06/27/2002 | US20020080666 Semiconductor memory device |
| 06/27/2002 | US20020080657 Semiconductor memory device and method for its test |
| 06/27/2002 | US20020080656 Method of using an integrated circuit |
| 06/27/2002 | US20020080652 Enhanced special programming mode |
| 06/27/2002 | US20020080640 Dynamic RAM-and semiconductor device |
| 06/27/2002 | US20020080639 256 Meg dynamic random access memory |