| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) |
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| 08/22/2002 | US20020116676 System and method to predetermine a bitmap of a self-tested embedded array |
| 08/22/2002 | US20020116673 Method and apparatus for testing memory |
| 08/22/2002 | US20020116672 Pattern data transmission device and pattern data transmission method |
| 08/22/2002 | US20020116668 Memory card with enhanced testability and methods of making and using the same |
| 08/22/2002 | US20020114203 Semiconductor integrated circuit with variable bit line precharging voltage |
| 08/22/2002 | US20020114202 Method and apparatus for testing memory |
| 08/22/2002 | US20020114201 Semiconductor memory circuit |
| 08/22/2002 | US20020114198 Semiconductor storage device formed to optimize test technique and redundancy technology |
| 08/22/2002 | US20020113254 Semiconductor memory device |
| 08/22/2002 | US20020113251 Redundant circuit and method for replacing defective memory cells in a memory device |
| 08/21/2002 | EP1233444A2 Membrane dielectric isolation ic fabrication |
| 08/21/2002 | EP1233422A1 Method and apparatus for refreshing reference cells |
| 08/21/2002 | EP1232399A1 High-speed failure capture apparatus and method for automatic test equipment |
| 08/21/2002 | CN1365148A Semiconductor storage device with tediously long system |
| 08/20/2002 | US6438719 Memory supervision |
| 08/20/2002 | US6438718 Wordline stress mode arrangement a storage cell initialization scheme test time reduction burn-in elimination |
| 08/20/2002 | US6438706 On chip error correction for devices in a solid state drive |
| 08/20/2002 | US6438667 Semiconductor memory and memory system |
| 08/20/2002 | US6438159 Method and apparatus for margining error rate of multi-drop data buses |
| 08/20/2002 | US6438064 Semiconductor memory device capable of efficient memory cell select operation with reduced element count |
| 08/20/2002 | US6438056 Method and device for refreshing the memory content of a memory cell of a read-only memory |
| 08/20/2002 | US6438053 Integrated memory having memory cells and reference cells |
| 08/20/2002 | US6438049 Variable equilibrate voltage circuit for paired digit lines |
| 08/20/2002 | US6438048 Nonvolatile memory and high speed memory test method |
| 08/20/2002 | US6438047 Semiconductor memory device and method of repairing same |
| 08/20/2002 | US6438046 System and method for providing row redundancy with no timing penalty for built-in-self-repair (BISR) in high density memories |
| 08/20/2002 | US6438045 Redundancy mapping in a multichip semiconductor package |
| 08/20/2002 | US6438044 Semiconductor memory device and method of testing the same |
| 08/20/2002 | US6438013 Semiconductor integrated circuit and method for adjusting characteristics of the same |
| 08/20/2002 | US6437629 Semiconductor device with circuit for adjusting input/output terminal capacitance |
| 08/20/2002 | US6437590 Integrated semiconductor device with wafer-level burn-in circuit and function decision method of wafer-level burn-in circuit |
| 08/20/2002 | US6436741 Semiconductor integrated circuit device |
| 08/20/2002 | US6436725 Method of manufacturing semiconductor device using redundancy technique |
| 08/15/2002 | WO2002063819A1 Method for recording and storage of system information in multi-board solid-state storage systems |
| 08/15/2002 | WO2002063635A1 Methods for tracing faults in memory components |
| 08/15/2002 | WO2002063634A1 Method for testing a non-volatile memory and the use of such a method |
| 08/15/2002 | WO2002063632A1 Method and device for verifying a group of non-volatile memory cells |
| 08/15/2002 | US20020112205 Techniques for providing data within a data storage system |
| 08/15/2002 | US20020111697 Minimizing interaction costs among components of computer programs |
| 08/15/2002 | US20020110939 Semiconductor device and method of inspecting the same |
| 08/15/2002 | US20020110034 Input-output circuit and current control circuit of semiconductor memory device |
| 08/15/2002 | US20020110033 Programmable fuse and antifuse and method therefor |
| 08/15/2002 | US20020110031 Zero margin enable controlling apparatus and method of sense amplifier adapted to semiconductor memory device |
| 08/15/2002 | US20020110029 Integrated circuit memory devices with per-bit redundancy and methods of operation thereof |
| 08/15/2002 | US20020110027 Semiconductor data storing circuit device, method of checking the device and method of relieving the device from defective cell |
| 08/15/2002 | US20020110024 Method and apparatus for testing a write function of a dual-port static memory cell |
| 08/15/2002 | US20020110016 Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof |
| 08/15/2002 | US20020109522 Test system and test method of semiconductor device |
| 08/15/2002 | US20020109154 Integrated circuit memory devices providing per-bit redundancy and methods of operating same |
| 08/15/2002 | US20020109138 Programmable memory address and decode circuits with ultra thin vertical body transistors |
| 08/15/2002 | US20020108565 Apparatus and method for selectively restricting process fluid flow in semiconductor processing |
| 08/14/2002 | EP1231608A1 Built-in test circuit and method for an integrated circuit |
| 08/14/2002 | DE10154649A1 Halbleiterspeicherbauelement mit redundanten Zellen und Verfahren zur Durchführung eines Voralterungstests The semiconductor memory device with redundant cells, and methods for carrying out a burn-in test |
| 08/14/2002 | DE10102871A1 Halbleiterbauelement zum Anschluß an ein Testsystem A semiconductor device for connecting to a test system |
| 08/14/2002 | CN1363935A Semiconductor storaging device for shortening test time |
| 08/14/2002 | CN1363841A Examination method for integrated circuit |
| 08/13/2002 | US6434679 Architecture for vital data management in a multi-module machine and process for implementing an architecture of this type |
| 08/13/2002 | US6434078 Semiconductor device allowing external setting of internal power supply voltage generated by a voltage down converter at the time of testing |
| 08/13/2002 | US6434070 Semiconductor integrated circuit with variable bit line precharging voltage |
| 08/13/2002 | US6434068 Nonvolatile semiconductor memory with testing circuit |
| 08/13/2002 | US6434067 Semiconductor memory having multiple redundant columns with offset segmentation boundaries |
| 08/13/2002 | US6434066 Device and method for repairing a semiconductor memory |
| 08/13/2002 | US6434065 Semiconductor memory device of low power consumption |
| 08/13/2002 | US6434064 Semiconductor memory device having redundancy circuit for saving faulty memory cells |
| 08/13/2002 | US6434063 Method of repairing semiconductor memory, electron-beam memory repairing apparatus and redundancy memory circuit to which the method of repairing semiconductor memory is applicable |
| 08/13/2002 | US6434059 Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts |
| 08/13/2002 | US6434033 DRAM module and method of using SRAM to replace damaged DRAM cell |
| 08/13/2002 | US6433569 Apparatus for testing an integrated circuit in an oven during burn-in |
| 08/13/2002 | US6433568 Massive parallel semiconductor manufacturing test process |
| 08/08/2002 | WO2002061839A1 Semiconductor integrated circuit device |
| 08/08/2002 | WO2001095339A3 High speed protocol memory test head for a memory tester |
| 08/08/2002 | WO2001095117A3 Data processing system for high speed memory test |
| 08/08/2002 | US20020108075 Method for recording and storage of system information in multi-board solid-state storage systems |
| 08/08/2002 | US20020108073 System for and method of operating a programmable column fail counter for redundancy allocation |
| 08/08/2002 | US20020105847 Semiconductor memory device capable of switching reference voltage for generating intermediate voltage |
| 08/08/2002 | US20020105843 Semiconductor device with self refresh test mode |
| 08/08/2002 | US20020105840 Memory circuit having block address switching function |
| 08/08/2002 | US20020105832 Nonvolatile semiconductor memory device detecting sign of data transformation |
| 08/08/2002 | US20020105372 Method and apparatus providing final test and trimming for a power supply controller |
| 08/08/2002 | US20020105357 Digital data coincidence determining circuit |
| 08/08/2002 | DE10102432A1 Testschaltung zur analogen Messung von Bitleitungssignalen ferroelektrischer Speicherzellen Test circuit for analog measurement of bit line signals ferroelectric memory cells |
| 08/08/2002 | DE10102430A1 Testschaltung zum Zykeln ferroelektrischer Speicherzellen eines integrierten ferroelektrischen Speicherbausteins Test circuit for Zykeln ferroelectric memory cells of a ferroelectric memory module integrated |
| 08/08/2002 | DE10101999A1 Elektronische Testschaltung und Verfahren für das Testen eines Speicherbausteins Electronic test circuit and method for testing a memory device |
| 08/07/2002 | EP1229553A1 Testing method for a reading operation in a non volatile memory |
| 08/07/2002 | EP1228378A1 Method and apparatus for testing circuits with multiple clocks |
| 08/07/2002 | EP0800138B1 Control apparatus and method for a RAID storage subsystem |
| 08/07/2002 | CN1362741A Fuse-wire circuit |
| 08/07/2002 | CN1088898C Semiconductor storage device |
| 08/06/2002 | US6430717 Semiconductor integrated circuit device and method for monitoring its internal signal |
| 08/06/2002 | US6430709 Apparatus and method for diagnosing microcomputer memory |
| 08/06/2002 | US6430671 Address generation utilizing an adder, a non-sequential counter and a latch |
| 08/06/2002 | US6430101 Fuse circuit using anti-fuse and method for searching for failed address in semiconductor memory |
| 08/06/2002 | US6430100 Redundancy circuitry for repairing defects in packaged memory having registers |
| 08/06/2002 | US6430097 Semiconductor memory device enabling reduction of test time period |
| 08/06/2002 | US6430096 Method for testing a memory device with redundancy |
| 08/06/2002 | US6430094 Method for testing a memory device having two or more memory arrays |
| 08/06/2002 | US6430072 Embedded CAM test structure for fully testing all matchlines |
| 08/01/2002 | WO2002059902A1 Semiconductor device manufacturing method and semiconductor device |
| 08/01/2002 | WO2002029825A3 Method to descramble the data mapping in memory circuits |
| 08/01/2002 | WO2002017078A3 Burst read incorporating output based redundancy |