Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
11/2002
11/21/2002US20020171447 Test circuit
11/21/2002US20020170898 High-speed, precision, laser-based method and system for processing material of one or more targets within a field
11/21/2002DE19807237C2 Halbleiterbauelement-Testgerät The semiconductor device testing apparatus
11/21/2002DE10220970A1 Halbleiterspeichervorrichtung A semiconductor memory device
11/21/2002DE10119869A1 Schaltungsanordnung zum selektiven Übertragen von Informationen an einen Chip eines Wafers bei der Chipherstellung beziehungsweise Vorrichtung mit einer Nadelkarte Circuitry for selectively transmitting information to a chip of a wafer in chip manufacture or device with a probe card
11/20/2002EP1258008A2 Method for efficient analysis of semiconductor failures
11/20/2002EP1257939A2 An efficient memory allocation scheme for data collection
11/20/2002CN1380659A Semiconductor memory device and method for selecting multi-word-line in said device
11/19/2002US6484289 Parallel data test for a semiconductor memory
11/19/2002US6484282 Test pattern generator, a memory testing device, and a method of generating a plurality of test patterns
11/19/2002US6484278 Method and apparatus for testing an embedded DRAM
11/19/2002US6484277 Integrated memory having a redundancy function
11/19/2002US6484271 Memory redundancy techniques
11/19/2002US6483773 Method for generating memory addresses for testing memory devices
11/19/2002US6483771 Semiconductor memory device and method of operation having delay pulse generation
11/19/2002US6483761 Semiconductor memory device
11/19/2002US6483760 Semiconductor memory integrated circuit operating at different test modes
11/19/2002US6483759 Methods for testing a group of semiconductor devices simultaneously, and devices amenable to such methods of testing
11/19/2002US6483758 Integrated circuit test systems that use direct current signals and impedance elements to improve test signal transmission speed and reduce test signal distortion
11/19/2002US6483755 Memory modules with high speed latched sense amplifiers
11/19/2002US6483745 Non-volatile semiconductor memory device with defect detection
11/19/2002US6483165 Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation
11/14/2002WO2002091111A2 Parity mirroring between controllers in an active-active controller pair
11/14/2002WO2002091006A1 Method for measuring fuse resistance in a fuse array
11/14/2002US20020170023 Method and apparatus for supplying current to a semiconductor memory chip
11/14/2002US20020170017 Parity mirroring between controllers in an active-active controller pair
11/14/2002US20020170015 System and method for performing backward error recovery in a computer
11/14/2002US20020170014 Apparatus and method to facilitate self-correcting memory
11/14/2002US20020170012 Address generator for generating addresses for testing a circuit
11/14/2002US20020170003 Semiconductor memory
11/14/2002US20020169922 Read/write timing calibration of a memory array using a row or a redundant row
11/14/2002US20020168815 Which has a manufacture-related memory cell defect pattern formed of defective memory cells, by using the memory cell defect pattern to generate a circuit identification number for the integrated circuit
11/14/2002US20020167859 Precharge control signal generator, and semiconductor memory device using the same
11/14/2002US20020167855 Fuse latch array system for an embedded dram having a micro-cell architecture
11/14/2002US20020167852 Full Stress open digit line memory device
11/14/2002US20020167850 Semiconductor memory device having row repair circuitry
11/14/2002US20020167849 Semiconductor memory device and testing method therefor
11/14/2002US20020167847 Semiconductor memory device having test mode
11/14/2002US20020167838 Resistive cross point memory with on-chip sense amplifier calibration method and apparatus
11/14/2002US20020167581 Methods and systems for thermal-based laser processing a multi-material device
11/14/2002US20020167323 Method for measuring fuse resistance in a fuse array
11/14/2002US20020167055 Semiconductor device
11/14/2002US20020166845 Methods and systems for precisely relatively positioning a waist of a pulsed laser beam and method and system for controlling energy delivered to a target structure
11/14/2002DE10124735C1 Semiconductor chip testing method has test mode status of initiated test mode read out via proof mode before execution of test mode
11/14/2002DE10121309A1 Test circuit for synchronous integrated circuits, especially memory (DRAM) chips whereby test errors due to signal transfer time differences are minimized and the circuit is insensitive to signal voltage potential variations
11/13/2002CN1379878A Redundant dual bank architecture for simultaneous operation flash memory
11/13/2002CN1379410A Semiconductor storage device
11/13/2002CN1379407A Semiconductor storage device having effective and reliable redundancy process
11/12/2002US6480982 Computer RAM memory system with enhanced scrubbing and sparing
11/12/2002US6480979 Semiconductor integrated circuits and efficient parallel test methods
11/12/2002US6480978 Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons
11/12/2002US6480799 Method and system for testing RAMBUS memory modules
11/12/2002US6480435 Semiconductor memory device with controllable operation timing of sense amplifier
11/12/2002US6480433 Dynamic random access memory with differential signal on-chip test capability
11/12/2002US6480432 Flash memory device having mask ROM cells for self-test
11/12/2002US6480431 Semiconductor having mechanism capable of operating at high speed
11/12/2002US6480430 Semiconductor device making reliable initial setting
11/12/2002US6480429 Shared redundancy for memory having column addressing
11/12/2002US6480428 Redundant circuit for memory device
11/12/2002US6480415 Nonvolatile semiconductor memory device
11/12/2002US6480018 Charge gain stress test circuit for nonvolatile memory and test method using the same
11/12/2002US6479363 Semiconductor integrated circuit and method for testing the same
11/12/2002US6479306 Method for manufacturing semiconductor device
11/07/2002WO2002089147A2 Circuit and method for memory test and repair
11/07/2002WO2002089146A2 Method of testing embedded memory array and embedded memory test controller for use therewith
11/07/2002WO2002089133A2 Data integrity error handling in a redundant storage array
11/07/2002US20020166086 Method and apparatus for testing memory cells for data retention faults
11/07/2002US20020165901 Characterization of objects of a computer program while running same
11/07/2002US20020165706 Memory controller emulator
11/07/2002US20020163850 Circuit and method for generating internal command signals in a semiconductor memory device
11/07/2002US20020163019 Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits
11/07/2002US20020162973 Methods and systems for processing a device, methods and systems for modeling same and the device
11/07/2002DE10217609A1 Ein-Chip-Mikrocomputer mit dynamischer Einbrenn-Testfunktion und dynamisches Einbrenn-Testverfahren dafür A one-chip microcomputer with a dynamic burn-in test function and dynamic burn-in test method therefor
11/07/2002DE10215117A1 Thin film magnetic memory suitable for stable data read-out and writing
11/07/2002DE10153892A1 Halbleiterspeichervorrichtung zur gleichzeitigen Eingabe von N Datensignalen Semiconductor memory device for simultaneous input of N data signals
11/07/2002DE10120670A1 Method for repairing hardware faults in memory components of a data processor
11/07/2002DE10120668A1 Testing of high speed memory chips by application of a test pattern to both the memory under test and a reference memory chip and then comparison of the contents of the two memory chips
11/07/2002DE10120255A1 Determination of the position of defective memory cells in a memory chip so that they can be replaced by redundant memory cells by provision of self test capability and use of a parallel to serial converter with a buffer memory
11/06/2002EP1255197A2 System and method for correcting soft errors in random access memory devices
11/06/2002EP1254461A1 Testable rom chip for a data memory redundant logic
11/06/2002CN1378139A Treating method and system for local defect internal memory
11/05/2002US6477676 Intermediate stage of a multi-stage algorithmic pattern generator for testing IC chips
11/05/2002US6477673 Structure and method with which to generate data background patterns for testing random-access-memories
11/05/2002US6477672 Memory testing apparatus
11/05/2002US6477671 Semiconductor memory, memory device, and memory card
11/05/2002US6477662 Apparatus and method implementing repairs on a memory device
11/05/2002US6477102 Redundant programmable circuit and semiconductor memory device having the same
11/05/2002US6477096 Semiconductor memory device capable of detecting memory cell having little margin
11/05/2002US6477095 Method for reading semiconductor die information in a parallel test and burn-in system
11/05/2002US6477094 Memory repair circuit using antifuse of MOS structure
11/05/2002US6477090 Semiconductor device, microcomputer and flash memory
11/05/2002US6477081 Integrated memory having memory cells with a magnetoresistive storage property
11/05/2002US6477075 Memory circuit/logic circuit integrated device capable of reducing term of works
11/05/2002US6477073 256 meg dynamic random access memory
11/05/2002US6477072 Layout design method on semiconductor chip for avoiding detour wiring
10/2002
10/31/2002WO2002086907A1 Integrated circuit with self-test device for an embedded non-volatile memory and related test method
10/31/2002WO2002086906A2 Method for the comparison of the address of a memory access with the already known address of a defective memory cell
10/31/2002WO2002086720A2 Method and apparatus for updating an error-correcting code during a partial line store
10/31/2002WO2002086719A2 Improved error correction scheme for use in flash memory allowing bit alterability
10/31/2002US20020162070 Dynamic error correction code shortening
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