Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
10/2002
10/31/2002US20020162069 System and method for correcting soft errors in random access memory devices
10/31/2002US20020162064 RAM functional test facilitation circuit with reduced scale
10/31/2002US20020162062 Device to inhibit duplicate cache repairs
10/31/2002US20020162061 Methods for tracing faults in memory components
10/31/2002US20020162060 Integrated circuit facilitating its unit test
10/31/2002US20020162046 Algorithmically programmable memory tester with history FIFO's that aid in ERROR analysis and recovery
10/31/2002US20020161963 Single-chip microcomputer with dynamic burn-in test function and dynamic burn-in testing method therefor
10/31/2002US20020160558 Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested
10/31/2002US20020159317 MRAM semiconductor memory configuration with redundant cell arrays
10/31/2002US20020159310 System of performing a repair analysis for a semiconductor memory device having a redundant architecture
10/31/2002US20020159308 Method and device for refreshing reference cells
10/31/2002US20020159305 Semiconductor device including built-in redundancy analysis circuit for simultaneously testing and analyzing failure of a plurality of memories and method for analyzing the failure of the plurality of memories
10/31/2002US20020159303 Asynchronous, High-bandwidth memory component using calibrated timing elements
10/31/2002US20020159293 Higher program vt and faster programming rates based on improved erase methods
10/31/2002US20020158271 Semiconductor integrated circuit
10/31/2002US20020158052 Method and system for processing one or more microstructures of a multi-material device
10/31/2002DE10217303A1 Algorithmisch programmierbarer Speichertester mit Unterbrechungspunktauslöser, Fehlerblockierung und Oszilloskop-Modus, der Zielsequenzen speichert Algorithmically programmable memory tester with breakpoint trigger fault blocking and oscilloscope mode, the target sequences stores
10/31/2002DE10119142A1 Method for detecting and repairing faulty addresses in semiconductor modules, esp. memory modules, involves applying lead voltage when at end of test procedure, at least one faulty address is present in latches
10/30/2002EP1253600A2 Memory tester
10/30/2002EP1253521A2 Method and apparatus for signaling between devices of a memory system
10/30/2002EP1071994B1 Storage device with redundant storage cells and method for accessing redundant storage cells
10/30/2002CN1377503A Method and circuit for evaluating information content of memory cell
10/30/2002CN1093662C Renumbered array architecture for multi-array memories
10/30/2002CN1093641C Memory testing apparatus
10/30/2002CA2345605A1 Method of testing embedded memory array and embedded memory controller for use therewith
10/29/2002US6473873 Semiconductor memory device
10/29/2002US6473872 Address decoding system and method for failure toleration in a memory bank
10/29/2002US6473828 Virtual channel synchronous dynamic random access memory
10/29/2002US6473722 Compact fault detecting system capable of detecting fault without omission
10/29/2002US6473360 Synchronous semiconductor memory device capable of high speed reading and writing
10/29/2002US6473358 Semiconductor memory device
10/29/2002US6473352 Semiconductor integrated circuit device having efficiently arranged link program circuitry
10/29/2002US6473347 Semiconductor device having memory with effective precharging scheme
10/29/2002US6473346 Self burn-in circuit for semiconductor memory
10/29/2002US6473345 Semiconductor memory device which can be simultaneously tested even when the number of semiconductor memory devices is large and semiconductor wafer on which the semiconductor memory devices are formed
10/29/2002US6473344 Semiconductor memory device capable of outputting a wordline voltage via an external pin
10/29/2002US6473339 Redundancy architecture for an interleaved memory
10/24/2002WO2002084669A1 System and method for erase test of integrated circuit device having non-homogeneously sized sectors
10/24/2002WO2002084668A1 Method and system to optimize test cost and disable defects for scan and bist memories
10/24/2002WO2002028162A3 Penalty free address decoding scheme
10/24/2002US20020157056 Method and apparatus for updating an error-correcting code during a partial line store
10/24/2002US20020157052 Test data generator
10/24/2002US20020157049 Method for testing semiconductor memory modules
10/24/2002US20020157048 Memory with element redundancy
10/24/2002US20020157047 Logical verification apparatus and method for memory control circuit
10/24/2002US20020157042 Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences
10/24/2002US20020157038 SRAM row redundancy
10/24/2002US20020156967 Semiconductor memory device
10/24/2002US20020154560 Integrated memory and method for testing an integrated memory
10/24/2002US20020154559 Semiconductor device, system, and method of controlling accessing to memory
10/24/2002US20020154553 System and method for redundancy implementation in a semiconductor device
10/24/2002US20020154551 Program components having multiple selectable implementations
10/24/2002US20020154536 Multi-function serial I/O circuit
10/24/2002US20020154534 Method and circuit for determining sense amplifier sensitivity
10/24/2002US20020153918 Circuit configuration for selectively transmitting information items from a measuring device to chips on a wafer during chip fabrication
10/24/2002US20020153917 Semiconductor integrated circuit and a method of testing the same
10/24/2002US20020153525 Semiconductor device with process monitor circuit and test method thereof
10/24/2002DE10209606A1 Pseudozufallssignal-Erzeugerschaltkreis Pseudo random signal generating circuit
10/24/2002DE10117891A1 Integrierter Taktgenerator, insbesondere zum Ansteuern eines Halbleiterspeichers mit einem Testsignal An integrated clock generator, in particular for driving a semiconductor memory with a test signal
10/24/2002DE10115280A1 Automated method for classifying electronic components according to their operating speed in which test results are stored in a database together with a component identifier so that the testing sequence is unimportant
10/24/2002DE10111440A1 Generator of addresses for testing circuit has addition stage that adds address applied to first input with relative address applied to second input to address stored in base address register
10/23/2002EP1251525A1 Semiconductor memory device, system, and method of controlling accessing to memory
10/23/2002EP1251522A2 Semiconductor memory device
10/23/2002EP1251520A2 Random access memory
10/23/2002EP1019910B1 Selective power distribution circuit for an integrated circuit
10/23/2002CN1375830A Semiconductor storage apparatus
10/23/2002CN1375829A Semiconductor storage adopting reductant mode
10/22/2002US6470479 Method of verifying semiconductor integrated circuit reliability and cell library database
10/22/2002US6470467 Synchronous semiconductor memory device capable of performing operation test at high speed while reducing burden on tester
10/22/2002US6470466 Integration type input circuit and method of testing it
10/22/2002US6470465 Parallel test circuit of semiconductor memory device
10/22/2002US6469949 Fuse latch array system for an embedded DRAM having a micro-cell architecture
10/22/2002US6469946 Semiconductor memory and its test method
10/22/2002US6469945 Dynamically configurated storage array with improved data access
10/22/2002US6469944 Method of compensating for a defect within a semiconductor device
10/22/2002US6469943 Switching circuit and semiconductor device
10/22/2002US6469932 Memory with row redundancy
10/22/2002US6469930 Compact nonvolatile circuit having margin testing capability
10/22/2002US6469923 Semiconductor device with programming capacitance element
10/22/2002US6469573 Semiconductor integrated circuit
10/22/2002US6469327 Semiconductor device with efficiently arranged pads
10/17/2002US20020152439 Method of outputting internal information through test pin of semiconductor memory and output circuit thereof
10/17/2002US20020152435 System and method for erase test of integrated circuit device having non-homogeneously sized sectors
10/17/2002US20020152434 SOI cell stability test method
10/17/2002US20020152351 Memory control circuit
10/17/2002US20020152349 Method and apparatus for file management
10/17/2002US20020149991 Test circuit for testing semiconductor memory
10/17/2002US20020149983 Methods for testing a group of semiconductor devices simultaneously, and devices amenable to such methods of testing
10/17/2002US20020149982 Memory device tester and method for testing reduced power states
10/17/2002US20020149981 Memory device tester and method for testing reduced power states
10/17/2002US20020149980 Built-in programmable self-diagnostic circuit for SRAM unit
10/17/2002US20020149979 Method for identifying an integrated circuit and integrated circuit
10/17/2002US20020149975 Testing device for testing a memory
10/17/2002US20020149972 Analog-to-digital converter for monitoring vddq and dynamically updating programmable vref when using high-frequency receiver and driver circuits for commercial memory
10/17/2002US20020149971 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other
10/17/2002US20020149966 Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing
10/17/2002US20020149959 Common module for ddr sdram and sdram
10/17/2002US20020149957 256 meg dynamic random access memeory
10/17/2002US20020149391 Antifuse reroute of dies
10/17/2002US20020149013 Semiconductor device with test mode
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