Patents
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
09/2002
09/12/2002US20020126546 Apparatus and method for securing recording medium driver
09/12/2002US20020126530 Coupling coefficient measuring method and coupling coefficient measuring apparatus for semiconductor memory
09/12/2002US20020126529 Memory with row redundancy
09/12/2002US20020126525 Circuit configuration for evaluating the information content of a memory cell
09/12/2002US20020125879 Parallel test board used in testing semiconductor memory devices
09/12/2002US20020125517 Ferroelectric capacitor and ferroelectric memory
09/12/2002DE10206720A1 System und Verfahren zum Betreiben eines programmierbaren Zählers für Spaltenversagen bei Redundanzzuordnung System and method for operating a programmable counter for the columns in redundancy allocation failure
09/12/2002DE10206719A1 Cache-Testsequenz für eintorigen Zeilenreparatur-CAM Cache test sequence for eintorigen row repair-CAM
09/12/2002DE10106557A1 Test device for parallel high frequency testing of semiconductor devices has signals transmitted via optical waveguides to and from devices under test
09/11/2002EP0884680B1 ROM testing circuit
09/11/2002CN1368737A Semiconductor data storage circuit device and its checking method and method for alternating badly element in said device
09/11/2002CN1368734A Semiconductor memory capable of control work timing of read amplifier
09/10/2002US6449740 Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode
09/10/2002US6449730 Loosely coupled mass storage computer cluster
09/10/2002US6449704 Memory failure analysis device that records which regions have at least one defect
09/10/2002US6449208 Semiconductor memory device capable of switching reference voltage for generating intermediate voltage
09/10/2002US6449204 Dynamic semiconductor memory device capable of rearranging data storage from a one bit/one cell scheme in a normal mode to a one bit/two cell scheme in a twin-cell mode for lengthening a refresh interval
09/10/2002US6449200 Duty-cycle-efficient SRAM cell test
09/10/2002US6449199 Semiconductor memory device with improved flexible redundancy scheme
09/06/2002WO2002069347A2 Flash cell fuse circuit
09/06/2002WO2002069343A1 Magnetoresistive midpoint generator
09/05/2002US20020124225 Multitrack data recording and read out of recorded multitrack digital data for error correction
09/05/2002US20020124219 Pseudo random signal producing circuit
09/05/2002US20020124209 Method and apparatus for saving data used in error analysis
09/05/2002US20020124203 Method for utilizing DRAM memory
09/05/2002US20020122343 Semiconductor storage device having redundancy circuit for replacement of defect cells under tests
09/05/2002US20020122342 Methods for forming aligned fuses disposed in an integrated circuit
09/05/2002US20020122341 Integrated memory and method for testing and repairing the integrated memory
09/05/2002US20020122337 Content addressable memory having redundant circuit
09/05/2002US20020122334 Flash memory device with cell current measuring scheme using write driver
09/05/2002DE10160092A1 Integrierte Halbleiterschaltungsvorrichtung A semiconductor integrated circuit device
09/05/2002DE10107664A1 Kontaktanordnung mit einer dielektrischen Fuse für ein IC-Speicherelement und Verfahren zur Herstellung einer solchen Kontaktanordnung Contact arrangement having a dielectric Fuse for an integrated circuit memory element and method of manufacturing such a contact arrangement
09/04/2002EP1236207A2 Architecture with multi-instance redundancy implementation
09/04/2002EP1236051A2 Bit fail map compression with fail signature analysis
09/04/2002EP1141834B1 Ic memory having a redundancy
09/04/2002EP0832486B1 Nonvolatile memory blocking architecture and redundancy
09/04/2002CN1367493A Connection washer device of electronic circuit
09/03/2002US6446241 Automated method for testing cache
09/03/2002US6446237 Updating and reading data and parity blocks in a shared disk system
09/03/2002US6446228 Semiconductor integrated circuit testing apparatus and method of controlling the same
09/03/2002US6446227 Semiconductor memory device
09/03/2002US6445641 Memory device with time shared data lines
09/03/2002US6445637 Semiconductor memory device with a refresh function
09/03/2002US6445630 Method for carrying out a burn-in process for electrically stressing a semiconductor memory
09/03/2002US6445629 Method of stressing a memory device
09/03/2002US6445627 Semiconductor integrated circuit
09/03/2002US6445626 Column redundancy architecture system for an embedded DRAM
09/03/2002US6445625 Memory device redundancy selection having test inputs
09/03/2002US6445614 Accelerated testing method and circuit for non-volatile memory
09/03/2002US6445604 Channel driving circuit of virtual channel DRAM
09/03/2002US6445558 Semiconductor integrated circuit device having pseudo-tuning function
08/2002
08/29/2002WO2002067263A2 Contact system comprising a dielectric antifuse for an ic-memory element and method for producing one such contact system
08/29/2002US20020120890 Efficient implementation of error correction code scheme
08/29/2002US20020120887 Cache test sequence for single-ported row repair CAM
08/29/2002US20020120826 Method and apparatus for reconfigurable memory
08/29/2002US20020120824 Method and system for data block sparing in a solid-state storage device
08/29/2002US20020118590 Semiconductor memory device with low power consumption
08/29/2002US20020118587 Semiconductor device
08/29/2002US20020118586 Integrated semiconductor memory device
08/29/2002US20020118585 Gate voltage testkey for isolation transistor
08/29/2002US20020118584 Semiconductor memory device
08/29/2002US20020118582 Log-structure array
08/29/2002US20020118581 Memory circuit redundancy control
08/29/2002US20020118580 Data compression read mode for memory testing
08/29/2002US20020118018 Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device
08/29/2002DE10158714A1 Halbleiterspeicher mit Spiegelfunktion Semiconductor memory with mirror function
08/29/2002DE10150509A1 Halbleiter-Datenspeicherschaltungseinrichtung, Verfahren zum Prüfen der Einrichtung, und Verfahren zum Befreien der Einrichtung von einer defekten Zelle Semiconductor data storage circuit means, method of testing the device, and method for freeing the device from a defective cell
08/29/2002DE10148904A1 Vorrichtung und Verfahren zur Steuerung der Abtastverstärkerfreigabe in einem Halbleiterspeicherbauelement Apparatus and method for controlling the Abtastverstärkerfreigabe in a semiconductor memory device
08/29/2002DE10145153A1 Halbleiterspeichervorrichtung mit steuerbarer Operationszeit des Leseverstärkers A semiconductor memory device having a controllable operating time of the sense amplifier
08/29/2002DE10132133A1 Statische Halbleiterspeichervorrichtung mit T-Typ-Bitleitungsstruktur Static semiconductor memory device with T-type bit line
08/29/2002DE10104716A1 Verfahren zum Testen eines Halbleiterspeichers und Halbleiterspeicher A method of testing a semiconductor memory and semiconductor memory
08/29/2002DE10104575A1 Verfahren zum Testen eines integrierten Speichers A method for testing an integrated memory
08/28/2002EP1235228A1 Semiconductor storage and method for testing the same
08/28/2002CN1366738A Interleave address generator
08/28/2002CN1366308A Semiconductor storage formed for optimizing testing technique and rebundance technique
08/27/2002US6442742 Cache memory having a DRAM memory cell
08/27/2002US6442733 Failure analyzing method and apparatus using two-dimensional wavelet transforms
08/27/2002US6442724 Failure capture apparatus and method for automatic test equipment
08/27/2002US6442723 Logic built-in self test selective signature generation
08/27/2002US6442722 Method and apparatus for testing circuits with multiple clocks
08/27/2002US6442719 Method and apparatus for detecting intercell defects in a memory device
08/27/2002US6442718 Memory module test system with reduced driver output impedance
08/27/2002US6442717 Parallel bit testing circuits and methods for integrated circuit memory devices including shared test drivers
08/27/2002US6442716 Data output buffer
08/27/2002US6442500 Devices for controlling temperature indications in integrated circuits using adjustable threshold temperatures
08/27/2002US6442101 Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts
08/27/2002US6442097 Virtual channel DRAM
08/27/2002US6442094 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
08/27/2002US6442086 Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
08/27/2002US6442085 Self-Test pattern to detect stuck open faults
08/27/2002US6442084 Semiconductor memory having segmented row repair
08/27/2002US6442083 Redundancy memory circuit
08/27/2002US6442074 Tailored erase method using higher program VT and higher negative gate erase
08/27/2002US6442069 Differential signal path for high speed data transmission in flash memory
08/27/2002US6442063 Integrated memory having memory cells with magnetoresistive memory effect
08/27/2002US6442056 Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices
08/27/2002US6442009 Semiconductor device having protective and test circuits
08/27/2002US6441627 Socket test device for detecting characteristics of socket signals
08/22/2002WO2002065476A1 Programmable fuse and antifuse and method therefor
08/22/2002WO2002050840A3 Data processing device with a write once memory (wom)