G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation

Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
12/2002
12/05/2002	US20020184604 Coordinate transformation system for semiconductor device, coordinate transformation method and coordinate transformation program
12/05/2002	US20020184586 MISR simulation tool for memory BIST application
12/05/2002	US20020184585 Apparatus and method for multi-cycle memory access mapped to JTAG finite state machine with external flag for hardware emulation
12/05/2002	US20020184578 Semiconductor integrated circuit
12/05/2002	US20020184557 System and method for memory segment relocation
12/05/2002	US20020183955 Test device for dynamic memory modules
12/05/2002	US20020182800 Semiconductor memory device
12/05/2002	US20020181309 Enhanced fuse configurations for low-voltage flash memories
12/05/2002	US20020181303 Semiconductor memory device
12/05/2002	US20020181302 Memory module, method for activating a memory cell, and method for repairing a defective memory cell
12/05/2002	US20020181301 Semiconductor storage and method for testing the same
12/05/2002	US20020181300 Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts
12/05/2002	US20020181296 Method of characterizing a delay locked loop
12/05/2002	US20020181285 Nonvolatile storage system
12/05/2002	US20020181281 Memory with row redundancy
12/05/2002	US20020181280 Nonvolatile semiconductor memory device and electronic information apparatus
12/05/2002	US20020181270 Configuration for evaluating a signal which is read from a ferroelectric storage capacitor
12/05/2002	US20020180543 Clock generation circuits and integrated circuit memory devices for controlling a clock period based on temperature and methods for using the same
12/05/2002	US20020179943 Semiconductor integrated circuit device
12/05/2002	DE10125029A1 Semiconducting device has contact devices externally contactable for making at least one temporary electrical signal connection between main and auxiliary integrated circuits
12/05/2002	DE10119052C1 Integrierter Speicher und Verfahren zum Testen eines integrierten Speichers Integrated memory and method for testing an integrated memory
12/04/2002	EP1262996A1 Semiconductor integrated circuit device
12/04/2002	EP1261972A1 Apparatus for testing memories with redundant storage elements
12/04/2002	EP1261919A2 Address decoding system and method for failure tolerance in a memory bank
12/04/2002	EP1163679B1 Method of operating an integrated memory with writable memory cells and corresponding integrated memory
12/04/2002	EP1084497B1 On-chip circuit and method for testing memory devices
12/04/2002	EP0842515B1 Memory system having non-volatile data storage structure for memory control parameters and method
12/04/2002	CN1383156A Single chip processor with dynamic ageing testing function and dynamic ageing testing method
12/04/2002	CN1383155A Thin film magnet memory able to stable read out datas and write in datas
12/04/2002	CN1383154A Multifunctional serial entry/output circuit
12/03/2002	US6490701 Integrated circuit test mode with externally forced reference voltage
12/03/2002	US6490700 Memory device testing apparatus and data selection circuit
12/03/2002	US6490697 Diagnosing apparatus and method for RAM
12/03/2002	US6490694 Electronic test system for microprocessor based boards
12/03/2002	US6490685 Storage device having testing function and memory testing method
12/03/2002	US6490223 Integrated circuit capable of being burn-in tested using an alternating current stress and a testing method using the same
12/03/2002	US6490222 Decoding circuit for controlling activation of wordlines in a semiconductor memory device
12/03/2002	US6490221 Semiconductor memory device with low power consumption
12/03/2002	US6490219 Semiconductor integrated circuit device and method of manufacturing thereof
12/03/2002	US6490210 Semiconductor memory integrated circuit employing a redundant circuit system for compensating for defectiveness
12/03/2002	US6490209 Memory employing multiple enable/disable modes for redundant elements and testing method using same
12/03/2002	US6490208 Column redundancy circuit
12/03/2002	US6490198 Test methods for semiconductor non-volatile memories
12/03/2002	US6490195 Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell
12/03/2002	US6490188 Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices
12/03/2002	US6489912 Analog-to-digital converter for monitoring VDDQ and dynamically updating programmable Vref when using high-frequency receiver and driver circuits for commercial memory
12/03/2002	US6489832 Chip information output circuit
12/03/2002	US6489819 Clock synchronous semiconductor memory device allowing testing by low speed tester
11/2002
11/28/2002	WO2002095802A2 Methods and apparatus for semiconductor testing
11/28/2002	WO2002095763A1 Test method for testing a data memory
11/28/2002	WO2002095759A1 Dynamically configured storage array utilizing a split-decoder
11/28/2002	WO2002095758A1 Dynamically configurated storage array with improved data access
11/28/2002	WO2002095756A2 Dynamic memory and method for testing a dynamic memory
11/28/2002	US20020178414 Synchronous flash memory with test code input
11/28/2002	US20020178413 Time data compression technique for high speed integrated circuit memory devices
11/28/2002	US20020178412 Memory testing method and apparatus, and computer-readable recording medium
11/28/2002	US20020178409 Method and apparatus for calibrating a test system for an integrated semiconductor circuit
11/28/2002	US20020177267 Semiconductor chip with trimmable oscillator
11/28/2002	US20020176310 Dynamically configured storage array utilizing a split-decoder
11/28/2002	US20020176306 Semiconductor memory and method of testing semiconductor memory
11/28/2002	US20020176303 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
11/28/2002	US20020176300 Refresh-circuit-containing semiconductor memory device
11/28/2002	US20020176297 Semiconductor memory device
11/28/2002	US20020176296 Semiconductor memory device and redundant output switch thereof
11/28/2002	US20020176295 Semiconductor memory device allowing easy characteristics evaluation
11/28/2002	US20020176294 Multi-bit parallel testing for memory devices
11/28/2002	US20020176292 Semiconductor integrated circuit device
11/28/2002	US20020176288 Semiconductor integrated circuit device and test method thereof
11/28/2002	US20020176287 Redundancy circuit of semiconductor memory device
11/28/2002	US20020175744 Semiconductor integrated circuit device including a negative power supply circuit
11/28/2002	US20020175742 Enhanced fuse configurations for low-voltage flash memories
11/28/2002	CA2448460A1 Methods and apparatus for semiconductor testing
11/27/2002	EP1260988A2 Resistive cross point memory device with calibration controller for a sense amplifier
11/27/2002	CN1382296A Method for identifying integrated circuit
11/27/2002	CN1381848A 地址生成电路 Address generation circuit
11/27/2002	CN1381847A 半导体存储器装置 The semiconductor memory device
11/27/2002	CN1095171C Auto-program circuit in nonvolatile semiconductor memory device
11/26/2002	US6487137 Semiconductor memory device having a second voltage supplier supplying transfer gates with a second voltage higher than a first voltage
11/26/2002	US6487131 Method and apparatus for testing a CAM addressed cache
11/26/2002	US6487129 Semiconductor apparatus
11/26/2002	US6487105 Test circuit for semiconductor integrated circuit which detects an abnormal contact resistance
11/26/2002	US6486731 Semiconductor integrated circuit device capable of externally monitoring internal voltage
11/26/2002	US6486651 Integrated circuit devices having a delay locked loop that is configurable for high-frequency operation during test and methods of operating same
11/26/2002	US6486493 Semiconductor integrated circuit device having hierarchical test interface circuit
11/21/2002	WO2002093584A1 Bist circuit with stored test results
11/21/2002	WO2002093583A1 Semiconductor memory test apparatus and method for address generation for defect analysis
11/21/2002	US20020174391 Method of testing semiconductor storage device
11/21/2002	US20020174386 Method and device for testing a memory circuit
11/21/2002	US20020174382 Multiple level built-in self-test controller and mehod therefor
11/21/2002	US20020174311 Method and apparatus for coordinating memory operations among diversely-located memory components
11/21/2002	US20020174289 Method and apparatus to enhance testability and validation of memory
11/21/2002	US20020174288 Methods for testing and programming nanoscale electronic devices
11/21/2002	US20020173926 Method and system for wafer and device-level testing of an integrated circuit
11/21/2002	US20020173055 For disconnecting (via cutting fuses) a defective memory cell; photoresists; semiconductors
11/21/2002	US20020172086 Memory device testing
11/21/2002	US20020172084 Column repair circuit of semiconductor memory
11/21/2002	US20020172083 Data memory
11/21/2002	US20020172073 Thin film magnetic memory device capable of conducting stable data read and write operations
11/21/2002	US20020171472 Voltage and time control circuits and methods of operating the same
11/21/2002	US20020171448 Dc testing apparatus and semiconductor testing apparatus

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