Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
06/2003
06/03/2003US6573524 Method of analyzing DRAM redundancy repair
05/2003
05/30/2003WO2003016922A3 Electronic circuit and method for testing
05/30/2003WO2002054411A9 Method for reading semiconductor die information in a parallel test and burn-in system
05/29/2003US20030101405 Semiconductor memory device
05/29/2003US20030101392 Method of testing memory with continuous, varying data
05/29/2003US20030101389 Method for reconfiguring a memory
05/29/2003US20030101388 System and method for avoiding waiting repair analysis for semiconductor testing equipment
05/29/2003US20030101376 Built-in self-testing for double data rate input/output
05/29/2003US20030101374 Semiconductor device with reduced terminal input capacitance
05/29/2003US20030101370 Integrated memory and method of repairing an integrated memory
05/29/2003US20030101313 Memory system
05/29/2003US20030099143 Memory circuit having compressed testing function
05/29/2003US20030099141 Semiconductor device having PLL-circuit
05/29/2003US20030099139 Memory test apparatus and method of testing
05/29/2003US20030099136 Semiconductor memory device
05/29/2003US20030099132 Semiconductor memory device including bit select circuit
05/29/2003US20030099130 Thin film magnetic memory device having a redundant structure
05/29/2003US20030099129 Data processing system, method, and product for automatically performing timing checks on a memory cell using a static timing tool
05/29/2003US20030098693 Apparatus for identifying state-dependent, defect-related leakage currents in memory circuits
05/29/2003US20030098456 Semiconductor integrated circuit and a testing method thereof
05/28/2003EP1315176A2 Memory circuit having parity cell array
05/28/2003EP1315175A2 Memory system
05/28/2003EP1315174A2 Semiconductor memory
05/28/2003EP1315173A1 Test method for ferroelectric memory
05/28/2003EP1315171A2 Non-volatile semiconductor memory device and memory system using the same
05/28/2003EP1314087A1 Nonvolatile fuse in redundancy circuit for low-voltage flash memories
05/28/2003CN1420565A 半导体存储器件 A semiconductor memory device
05/28/2003CN1420561A Semiconductor IC and mfg. method thereof
05/28/2003CN1420501A Semiconductor memory device and redundance judging method
05/28/2003CN1420499A 保护电路 Protection circuit
05/28/2003CN1419995A Machine for pick-up of devcie in processor
05/28/2003CN1110095C Semiconductor device and internal function identification method of semiconductor device
05/28/2003CN1110053C Method for writing data in EEPROM array
05/27/2003US6571364 Semiconductor integrated circuit device with fault analysis function
05/27/2003US6571353 Fail information obtaining device and semiconductor memory tester using the same
05/27/2003US6571352 Device for repairing a Semiconductor memory
05/27/2003US6571349 Loosely coupled mass storage computer cluster
05/27/2003US6571348 Method of and apparatus for providing look ahead column redundancy access within a memory
05/27/2003US6571324 Warmswap of failed memory modules and data reconstruction in a mirrored writeback cache system
05/27/2003US6570814 Integrated circuit device which outputs data after a latency period transpires
05/27/2003US6570808 Apparatus for selecting bank in semiconductor memory device
05/27/2003US6570806 System and method for improving DRAM single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor
05/27/2003US6570797 Design for test to emulate a read with worse case test pattern
05/27/2003US6570796 Wafer burn-in test and wafer test circuit
05/27/2003US6570794 Twisted bit-line compensation for DRAM having redundancy
05/27/2003US6570793 Semiconductor memory having a redundancy circuit for word lines and method for operating the memory
05/27/2003US6570790 Highly compact EPROM and flash EEPROM devices
05/22/2003WO2003043024A1 Test method for ferroelectric memories
05/22/2003WO2003043023A1 Method for the reconfiguration of a memory
05/22/2003WO2003043022A2 Memory unit test
05/22/2003WO2003019574A3 Method for the high-voltage screening of an integrated circuit
05/22/2003US20030097627 Field repairable embedded memory in system-on-a-chip
05/22/2003US20030097626 Method and system for performing memory repair analysis
05/22/2003US20030097623 Method and apparatus for performance optimization and adaptive bit loading for wireless modems with convolutional coder, FEC, CRC and ARQ
05/22/2003US20030097620 Semiconductor integrated circuit
05/22/2003US20030097609 Flash EEprom system
05/22/2003US20030095467 Test circuit for testing semiconductor memory
05/22/2003US20030095455 Semiconductor integrated circuit
05/22/2003US20030095451 Laser link structure capable of preventing an upper crack and broadening an energy window of a laser beam, and fuse box using the same
05/22/2003US20030095450 Nonvolatile semiconductor storage device and write time determining method therefor
05/22/2003US20030095449 Semiconductor memory device and redundancy judging method
05/22/2003US20030095438 Nonvolatile semiconductor memory device having function of determining good sector
05/22/2003US20030095433 Semiconductor device
05/22/2003US20030095430 Semiconductor memory device
05/22/2003US20030094995 Fuse circuit
05/21/2003EP1194849B1 A system and method for improving multi-bit error protection in computer memory systems
05/21/2003CN1419291A Nonvolatile semiconductor memory
05/21/2003CN1419278A Reference bit stabilizing method for multibit storage unit
05/21/2003CN1419274A 半导体电路装置及半导体装置 The semiconductor circuit device and semiconductor device
05/21/2003CN1419244A Fault-tolerant memory module circuit
05/21/2003CN1419243A 半导体存储器 Semiconductor memory
05/20/2003US6567953 Method and apparatus for host-based validating of data transferred between a device and a host
05/20/2003US6567950 Dynamically replacing a failed chip
05/20/2003US6567941 Event based test system storing pin calibration data in non-volatile memory
05/20/2003US6567940 Method of testing random-access memory
05/20/2003US6567939 Merged data line test circuit for classifying and testing a plurality of data lines, and test method performed by the same
05/20/2003US6567926 Loosely coupled mass storage computer cluster
05/20/2003US6567334 Storage device employing a flash memory
05/20/2003US6567333 Fuse circuit using anti-fuse and method for searching for failed address in semiconductor memory
05/20/2003US6567325 Apparatus and method for system access to tap controlled BIST of random access memory
05/20/2003US6567324 Semiconductor memory device with reduced number of redundant program sets
05/20/2003US6567323 Memory circuit redundancy control
05/20/2003US6567322 Semiconductor memory device
05/20/2003US6566937 Fuse circuit
05/20/2003US6566682 Programmable memory address and decode circuits with ultra thin vertical body transistors
05/20/2003US6566238 Metal wire fuse structure with cavity
05/15/2003WO2003041085A1 Dual mode high voltage power supply for providing increased speed in programming during testing of low voltage non-volatile memories
05/15/2003WO2003040922A2 Multibit package error correction with non-restricted double bit error etection
05/15/2003WO2003040738A1 Timing generator and test apparatus
05/15/2003WO2003040737A1 Test apparatus
05/15/2003WO2002089146A3 Method of testing embedded memory array and embedded memory test controller for use therewith
05/15/2003US20030093745 Method and apparatus of recording/reproducing data using a U-pattern scan
05/15/2003US20030093735 Apparatus and method for random pattern built in self-test
05/15/2003US20030093733 Modeling custom scan flops in level sensitive scan design
05/15/2003US20030093713 Multilevel signal interface testing with binary test apparatus by emulation of multilevel signals
05/15/2003US20030093711 Flash EEprom system
05/15/2003US20030090943 Semiconductor memory
05/15/2003US20030090942 Semiconductor device
05/15/2003US20030090941 Flash EEprom system
05/15/2003US20030090940 Dual mode high voltage power supply for providing increased speed in programming during testing of low voltage non-volatile memories
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