Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
10/2003
10/29/2003EP1357559A1 Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory device
10/29/2003EP1356473A1 Method and device for verifying a group of non-volatile memory cells
10/29/2003EP0726521B1 Disk array having hot spare resources and methods for using hot spare resources to store user data
10/29/2003CN1452316A Scanning path circuit and semiconductor IC contg. said scanning path circuit
10/29/2003CN1452183A Method for detection of flash memory logical bit address
10/29/2003CN1452181A NAND model flash memory magnetic disk device and method for detection of logical bit address
10/29/2003CN1126103C Fuse circuit and redundant decoder
10/28/2003US6640321 Built-in self-repair of semiconductor memory with redundant row testing using background pattern
10/28/2003US6640320 Hardware circuitry to speed testing of the contents of a memory
10/28/2003US6640198 Semiconductor device having self test function
10/28/2003US6639863 Semiconductor integrated circuit device having link element
10/28/2003US6639861 Integrated memory and method for testing an integrated memory
10/28/2003US6639860 Controlling temperature for first screening, controlling temperature at different level for second screening
10/28/2003US6639859 Test array and method for testing memory arrays
10/28/2003US6639858 Semiconductor memory device having defective memory block
10/28/2003US6639857 Coding cell of nonvolatile ferroelectric memory device and operating method thereof, and column repair circuit of nonvolatile ferroelectric memory device having the coding cell and method for repairing column
10/28/2003US6639856 Memory chip having a test mode and method for checking memory cells of a repaired memory chip
10/28/2003US6639855 Semiconductor device having a defect relief function of relieving a failure
10/28/2003US6639854 Redundancy circuit of semiconductor memory device
10/28/2003US6639853 Defect avoidance in an integrated circuit
10/28/2003US6639850 Semiconductor integrated circuit having latching means capable of scanning
10/28/2003US6639848 Semiconductor memory device and method for testing the same
10/28/2003US6639822 Dynamic ram-and semiconductor device
10/28/2003US6639177 Method and system for processing one or more microstructures of a multi-material device
10/23/2003WO2003088041A1 Methods for storing data in non-volatile memories
10/23/2003WO2002075337A3 Low-jitter clock for test system
10/23/2003US20030200498 Method for arranging data output by semiconductor testers to packet-based devices under test
10/23/2003US20030200491 Method for verifying and improving run-time of a memory test
10/23/2003US20030198116 Semiconductor memory device equipped with control circuit for controlling memory cell array in non-normal operation mode
10/23/2003US20030198111 6F2 DRAM array with apparatus for stress testing an isolation gate and method
10/23/2003US20030198109 Semiconductor memory device with series-connected antifuse-components
10/23/2003US20030198107 Method of checking the state of a capacitor fuse in which the voltage applied to the capacitor fuse is the same level as voltage applied to memory cells
10/23/2003US20030198103 Non-volatile semiconductor memory device
10/23/2003US20030198083 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
10/23/2003US20030198079 Memory IC
10/23/2003US20030198071 Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM)
10/23/2003US20030197545 Semiconductor circuit and initialization method
10/23/2003US20030197520 Systems and methods for facilitating driver strength testing of integrated circuits
10/23/2003US20030197515 Fault tolerant semiconductor system
10/23/2003CA2481492A1 Methods for storing data in non-volatile memories
10/22/2003EP1118937B1 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
10/22/2003EP1054326B1 Memory error correction using redundant sliced memory and standard ECC mechanisms
10/22/2003CN1450566A Method for quickly identifying element line defect kenel
10/22/2003CN1450565A Method for detecting memory by utilizing continuous data change
10/21/2003US6636998 Semiconductor memory device and parallel bit test method thereof
10/21/2003US6636985 Disk storage device and a method for processing defective sectors in a disk storage device
10/21/2003US6636937 System and method for safe high-temperature operation of a flash memory
10/21/2003US6636825 Component level, CPU-testable, multi-chip package using grid arrays
10/21/2003US6636455 Semiconductor memory device that operates in synchronization with a clock signal
10/21/2003US6636448 Semiconductor memory device having fewer memory cell plates being activated in a test mode than in a normal mode
10/21/2003US6636447 Memory module, method for activating a memory cell, and method for repairing a defective memory cell
10/16/2003WO2003085734A1 Interconnection structure and methods
10/16/2003WO2003085671A1 Method and apparatus for repairing defective columns of memory cells
10/16/2003US20030196143 Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories
10/16/2003US20030196051 Method for managing data stored primarily in a read-only memory
10/16/2003US20030196029 Method of writing, erasing, and controlling memory for memory device
10/16/2003US20030195714 Calibration of memory circuits
10/16/2003US20030193823 Semiconductor memory device provided with test memory cell unit
10/16/2003US20030193822 Redundant array architecture for word replacement in cam
10/15/2003EP1352397A1 Method for testing a non-volatile memory and the use of such a method
10/15/2003EP1352396A2 Method and apparatus for built-in self-repair of memory storage arrays
10/15/2003EP1173853B1 Failure capture apparatus and method for automatic test equipment
10/15/2003CN1448957A Method for testing memory apparatus
10/15/2003CN1448956A Method for testing non-volatile memory
10/15/2003CN1124607C Device and method of writing-in or reading-out data
10/14/2003US6634004 Threshold analysis system capable of deciding all threshold voltages included in memory device through single processing
10/14/2003US6634003 Decoding circuit for memories with redundancy
10/14/2003US6634002 Test circuit of semiconductor memory
10/14/2003US6633999 Integrated circuit with on-chip data checking resources
10/14/2003US6633507 Cancellation of redundant elements with a cancel bank
10/14/2003US6633504 Synchronous DRAM having test mode in which automatic refresh is performed according to external address and automatic refresh method
10/14/2003US6633502 Test device for semiconductor memory circuit
10/14/2003US6633183 Antifuse reroute of dies
10/14/2003US6633180 Methods of rerouting dies using antifuses
10/14/2003US6633014 Enhanced grading and sorting of semiconductor devices using modular “plug-in” sort algorithms
10/09/2003US20030191998 Built-in self test circuit
10/09/2003US20030191997 Device and method for testing integrated circuit dice in an integrated circuit module
10/09/2003US20030191995 System for communicating with synchronous device
10/09/2003US20030191994 Method for verifying the accuracy of bit-map memory test programs
10/09/2003US20030191993 Semiconductor device for memory test with changing address information
10/09/2003US20030191991 Flexible row redundancy system
10/09/2003US20030191983 Loosely coupled mass storage computer cluster
10/09/2003US20030191885 On-chip cache redundancy technique
10/09/2003US20030189845 Semiconductor device having redundancy circuit
10/09/2003US20030189436 Method and test structure for determining resistances at a plurality of interconnected resistors in an integrated circuit
10/08/2003EP1350254A2 Method for reading semiconductor die information in a parallel test and burn-in system
10/08/2003CN1447335A Multiport scanning chain register device and method
10/07/2003US6631492 Multitrack data recording and read out of recorded multitrack digital data for error correction
10/07/2003US6631340 Application specific event based semiconductor memory test system
10/07/2003US6631092 Semiconductor memory device capable of imposing large stress on transistor
10/07/2003US6631091 Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts
10/07/2003US6631086 On-chip repair of defective address of core flash memory cells
10/07/2003US6631084 256 Meg dynamic random access memory
10/07/2003US6630381 Preventing dielectric thickening over a floating gate area of a transistor
10/02/2003US20030188240 Multi-port scan chain register apparatus and method
10/02/2003US20030188238 Method and apparatus for providing adjustable latency for test mode compression
10/02/2003US20030188236 Method of testing memory device
10/02/2003US20030185074 Semiconductor memory device, method for testing same and semiconductor device
10/02/2003US20030185063 Method of quickly determining work line failure type
10/02/2003US20030185041 Semiconductor memory device
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