Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
10/2003
10/02/2003US20030185040 FeRAM with a single access/ multiple-comparison operation
10/02/2003US20030184335 Method of electrically testing semiconductor devices
10/01/2003EP1349176A1 Hardware and software programmable fuses for memory repair
10/01/2003EP1349171A1 Data exchange device between scan chains
10/01/2003CN1123010C ROM data verification circuit
09/2003
09/30/2003US6629281 Method and system for at speed diagnostics and bit fail mapping
09/30/2003US6629280 Method and apparatus for delaying ABIST start
09/30/2003US6629275 Reinstate apparatus and method to recreate data background for testing SRAM
09/30/2003US6629274 Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output buffer
09/30/2003US6629273 Detection of silent data corruption in a storage system
09/30/2003US6629190 Non-redundant nonvolatile memory and method for sequentially accessing the nonvolatile memory using shift registers to selectively bypass individual word lines
09/30/2003US6629052 Adjustment method for reducing channel skew of test system
09/30/2003US6628555 Semiconductor circuit having a detection circuit for controlling a power boosting circuit
09/30/2003US6628554 MIS semiconductor device having improved gate insulating film reliability
09/30/2003US6628536 Semiconductor memory device
09/30/2003US6628162 Semiconductor integrated circuit
09/30/2003US6628156 Integrated circuit having a timing circuit, and method for adjustment of an output signal from the timing circuit
09/30/2003US6628134 DC stress supply circuit
09/30/2003US6627558 Apparatus and method for selectively restricting process fluid flow in semiconductor processing
09/25/2003WO2003079556A1 System and method for forward error correction
09/25/2003WO2003079362A2 Circuit arrangement for sensing and evaluating a charge state and rewriting the latter to a memory cell
09/25/2003US20030182608 Method and apparatus for achieving higher product yields by using fractional portions of imbedded memory arrays
09/25/2003US20030182607 Semiconductor memory device and method of testing same
09/25/2003US20030182595 Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs)
09/25/2003US20030182531 Hardware and software programmable fuses for memory repair
09/25/2003US20030179644 Synchronous global controller for enhanced pipelining
09/25/2003US20030179643 Efficient column redundancy techniques
09/25/2003US20030179642 Distributed, highly configurable modular predecoding
09/25/2003US20030179641 Block redundancy implementation in heirarchical RAM's
09/25/2003US20030179640 Synchronous controlled, self-timed local sram block
09/25/2003US20030179636 Semiconductor memory test device
09/25/2003US20030179635 Burn in system and method for improved memory reliability
09/25/2003US20030179618 Internal voltage generating apparatus for a semiconductor memory device
09/25/2003US20030179616 Reducing Memory Failures in Integrated Circuits
09/24/2003EP1347459A1 Burn in system and method for improved memory reliability
09/24/2003EP1347457A2 Synchronous controlled, self-timed local SRAM block
09/24/2003EP1346364A2 Data processing device with a wom memory
09/24/2003EP1093586B1 Integrated circuit with improved synchronism for an external clock signal at a data output
09/24/2003CN1444743A Burst read incorporating output based redundancy
09/24/2003CN1444283A Integrated circuit for storage
09/24/2003CN1122283C Semiconductor storing apparatus and its driving method
09/24/2003CN1122280C Memory with stress circuitry for detecting defects
09/24/2003CN1122218C Logical check apparatus for semiconductor circuits
09/23/2003US6625766 Tester of semiconductor memory device and test method thereof
09/23/2003US6625748 Data reconstruction method and system wherein timing of data reconstruction is controlled in accordance with conditions when a failure occurs
09/23/2003US6625082 Test circuit for testing semiconductor memory
09/23/2003US6625076 Circuit configuration fir evaluating the information content of a memory cell
09/23/2003US6625073 Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices
09/23/2003US6625072 Semiconductor integrated circuit device provided with a self-testing circuit for carrying out an analysis for repair by using a redundant memory cell
09/23/2003US6625071 Memory circuit having block address switching function
09/23/2003US6625068 Apparatus for reducing bleed currents within a DRAM array having row-to-column shorts
09/23/2003US6625061 Method of managing a defect in a flash memory
09/18/2003WO2003032372A8 A three-dimensional memory
09/18/2003US20030177424 Semiconductor memory improved for testing
09/18/2003US20030177418 Test method and test apparatus for an electronic module
09/18/2003US20030177415 Self-testing circuit in semiconductor memory device
09/18/2003US20030174567 Integrated circuit memory devices having efficient multi-row address test capability and methods of operating same
09/18/2003US20030174566 Semiconductor memory device with enhanced reliability
09/18/2003US20030174561 Nonvolatile semiconductor memory device
09/18/2003US20030174560 Photochromic compounds for molecular switches and optical memory
09/18/2003US20030174558 Nonvolatile register and semiconductor device
09/18/2003US20030174556 Method and device for verifying a group of non-volatile memory cells
09/18/2003US20030173607 Semiconductor memory device
09/17/2003EP1105876A4 Method and apparatus for built-in self test of integrated circuits
09/17/2003CN1121696C Semiconductor memory device capable of realization stable test mode operation
09/17/2003CN1121693C Semiconductor storage device and test method thereof
09/16/2003US6622274 Method of micro-architectural implementation on bist fronted state machine utilizing ‘death logic’ state transition for area minimization
09/16/2003US6622270 System for optimizing anti-fuse repair time using fuse ID
09/16/2003US6622269 Memory fault isolation apparatus and methods
09/16/2003US6622205 Process for the secure writing of a pointer for a circular memory
09/16/2003US6622196 Method of controlling semiconductor memory device having memory areas with different capacities
09/16/2003US6622108 Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit
09/16/2003US6621755 Testmode to increase acceleration in burn-in
09/16/2003US6621751 Method and apparatus for programming row redundancy fuses so decoding matches internal pattern of a memory array
09/16/2003US6621750 Semiconductor memory
09/16/2003US6621749 Integrated circuit memory devices providing per-bit redundancy and methods of operating same
09/16/2003US6621748 Recovery of useful areas of partially defective synchronous memory components
09/16/2003US6621734 Nonvolatile semiconductor memory device and electronic information apparatus
09/16/2003US6621352 Semiconductor integrated circuit device
09/16/2003US6621283 Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit
09/12/2003WO2003075233A2 Smart card and method for avoiding software bug on such a smart card
09/11/2003US20030172339 Method for error correction decoding in a magnetoresistive solid-state storage device
09/11/2003US20030172330 Data redundancy in a hot pluggable, large symmetric multi-processor system
09/11/2003US20030172329 Allocation of sparing resources in a magnetoresistive solid-state storage device
09/11/2003US20030169633 Method of checking electrical connections between a memory module and a semiconductor memory chip
09/11/2003US20030169632 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
09/11/2003US20030169631 Semiconductor memory device with improved flexible redundancy scheme
09/11/2003US20030169628 Semiconductor memory device with redundant memory cells
09/11/2003US20030169621 Nonvolatile multilevel cell memory
09/11/2003US20030168681 Semiconductor integrated circuit device and characteristic measurement method thereof
09/10/2003EP1343174A2 Programmable test for memories
09/10/2003EP1343173A1 Prgrammable test for memories
09/10/2003EP1159630B1 Distributed interface for parallel testing of multiple devices using a single tester channel
09/10/2003EP0845788B1 A memory array test circuit with failure notification
09/10/2003CN1441437A Defect unit address programing circuit and method for programing defect unit address
09/10/2003CN1121042C Memory element testing circuit
09/09/2003US6618826 Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMs
09/09/2003US6618311 Zero power fuse sensing circuit for redundancy applications in memories
09/09/2003US6618310 Synchronous semiconductor memory device and refresh method thereof
09/09/2003US6618306 Semiconductor memory device having row and column redundancy circuit and method of manufacturing the circuit
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