Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
09/2003
09/09/2003US6618305 Test circuit for testing a circuit
09/09/2003US6618304 Memory module with test mode
09/09/2003US6618303 Integrated circuit, test structure and method for testing integrated circuits
09/09/2003US6618301 Modular memory structure having adaptable redundancy circuitry
09/09/2003US6618300 Semiconductor memory device and method for replacing redundancy circuit
09/09/2003US6618299 Semiconductor memory device with redundancy
09/09/2003US6618298 Semiconductor memory device
09/09/2003US6618288 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
09/09/2003US6618281 Content addressable memory (CAM) with error checking and correction (ECC) capability
09/09/2003US6618279 Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM)
09/09/2003US6617842 Semiconductor device testing method and system employing trace data
09/09/2003US6617610 Semiconductor integrated circuit
09/09/2003US6617179 Method and system for qualifying an ONO layer in a semiconductor device
09/09/2003US6617172 Semiconductor device having identification number, manufacturing method thereof and electronic device
09/04/2003WO2003073805A2 Improved patching methods and apparatus for fabricating memory modules
09/04/2003WO2003073434A1 Non-volatile memory test structure and method
09/04/2003WO2003073356A1 Memory module assembly using partially defective chips
09/04/2003WO2003071853A2 Removable memory media with integral indicator light
09/04/2003WO2002101749A9 Methods and apparatus for analyzing and repairing memory
09/04/2003US20030167439 Data integrity error handling in a redundant storage array
09/04/2003US20030167431 Programmable test for memories
09/04/2003US20030167428 ROM based BIST memory address translation
09/04/2003US20030167427 Partitionable embedded circuit test system for integrated circuit
09/04/2003US20030167426 Method and apparatus for memory self testing
09/04/2003US20030167372 Semiconductor memory device with a flexible redundancy scheme
09/04/2003US20030165077 Semiconductor memory device permitting early detection of defective test data
09/04/2003US20030164510 Redundancy architecture for repairing semiconductor memories
09/04/2003CA2477766A1 Improved patching methods and apparatus for fabricating memory modules
09/04/2003CA2477754A1 Memory module assembly using partially defective chips
09/03/2003EP1123556A4 Fuse circuit having zero power draw for partially blown condition
09/03/2003EP0889409B1 Mirrored write-back cache module warmswap
09/03/2003EP0843852B1 Method and apparatus for detecting duplicate entries in a look-up table
09/03/2003CN1440570A Automated determination and display of physical location of failed cell in array of memory cells
09/03/2003CN1440554A Method for performing write and read operations in passive matrix memmory, and apparatus for performing method
09/03/2003CN1120500C Semiconductor memory device having selection circuit
09/03/2003CN1120497C Auto power down circuit for semiconductor memory device
09/03/2003CN1120422C Method of making memory fault-tolerant using variable size redundancy replacement contiguration
09/03/2003CN1120421C Fault tolerant memory device
09/03/2003CN1120414C Deinterlacing device
09/02/2003US6615391 Current controlled multi-state parallel test for semiconductor device
09/02/2003US6615390 Method of manufacturing IC cards
09/02/2003US6615363 Optical disk and method of recording on the same
09/02/2003US6614713 Semiconductor memory device having a circuit for fast operation
09/02/2003US6614703 Method and system for configuring integrated systems on a chip
09/02/2003US6614701 Weak bit testing
09/02/2003US6614685 Flash memory array partitioning architectures
09/02/2003US6614259 Configuration memory integrated circuit
09/02/2003US6614254 Method for testing semiconductor integrated circuit device equipped with power make-up circuit used in burn-in test
09/02/2003US6613595 Test structure and method for flash memory tunnel oxide quality
09/02/2003US6612022 Printed circuit board including removable auxiliary area with test points
08/2003
08/28/2003WO2003071554A2 Non-volatile redundancy adresses memory
08/28/2003WO2002103706A3 System and method for identification of faulty or weak memory cells under simulated extreme operating conditions
08/28/2003US20030163777 Optimized read performance method using metadata to protect against drive anomaly errors in a storage array
08/28/2003US20030163776 Interleavers and de-interleavers
08/28/2003US20030163636 Circuit for implementing special mode in packet-based semiconductor memory device
08/28/2003US20030163218 Patching methods and apparatus for fabricating memory modules
08/28/2003US20030161205 Non-volatile memory with test rows for disturb detection
08/28/2003US20030161204 Semiconductor memory device capable of performing burn-in test at high speed
08/28/2003US20030161202 Semiconductor memory
08/28/2003US20030161199 Removable memory media with integral indicator light
08/28/2003US20030161198 Method and apparatus for implementing a selectively operable clock booster for DDR memory or other logic modules which utilize partially-defective memory parts, or a combination of partially-defective and flawless memory parts
08/28/2003US20030161176 Method for measuring bias voltage of sense amplifier in memory device
08/28/2003US20030160288 Method for storing data in a memory device with the possibility of access to redundant memory cells
08/27/2003EP1338014A1 AT-SPEED BUILT-IN SELF TESTING OF MULTI-PORT COMPACT sRAMs
08/27/2003EP1224549B1 Redundant dual bank architecture for a simultaneous operation flash memory
08/27/2003EP0801401B1 Testing and repair of embedded memory
08/27/2003CN1438707A Semiconductor storage device
08/27/2003CN1119816C Synchronous semiconductor storage device having timed circuit of controlling activation/non-activation of word line
08/27/2003CN1119815C One-chip clock synchronized memory device
08/27/2003CN1119809C Nonvolatile memory blocking arckitecture and redundancy
08/26/2003US6611938 Flash memory
08/26/2003US6611935 Method and system for efficiently testing circuitry
08/26/2003US6611931 Check method of temporary storage circuit in electronic control unit
08/26/2003US6611930 Linked lists diagnostics
08/26/2003US6611929 Test circuit for memory
08/26/2003US6611470 Semiconductor memory device having refresh size setting circuit
08/26/2003US6611469 Asynchronous FIFO memory having built-in self test logic
08/26/2003US6611467 Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
08/26/2003US6611466 Semiconductor memory device capable of adjusting the number of banks and method for adjusting the number of banks
08/26/2003US6611464 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics
08/26/2003US6611458 Semiconductor integrated circuit device
08/26/2003US6611445 Content addressable memory having redundant circuit
08/21/2003US20030159098 Method for generating test signals for an integrated circuit and test logic unit
08/21/2003US20030159095 Low cost built-in self test state machine for general purpose RAM testing
08/21/2003US20030156487 Semiconductor memory device including data bus pairs respectively dedicated to data writing and data reading
08/21/2003US20030156485 Semiconductor memory device having divided word line structure
08/21/2003US20030156477 Bypass circuits; calibration; faser fusion of resistors
08/21/2003US20030156475 Method and circuit for repairing nonvolatile ferroelectric memory device
08/21/2003US20030156469 Fuse concept and method of operation
08/21/2003US20030156456 Method for operating a memory device
08/21/2003US20030156442 Semiconductor memory device and multi-chip module comprising the semiconductor memory device
08/21/2003US20030155941 Systems and methods for testing a plurality of circuit devices
08/21/2003DE10201431C1 Integrierte Schaltung und Verfahren zum Betrieb einer Testanordnung mit einer integrierten Schaltung Integrated circuit and method for operating a test arrangement with an integrated circuit
08/20/2003EP0933708B1 Integrated storage featuring error correcting data in one operating mode
08/20/2003CN1437245A Method for proving program with fast program
08/20/2003CN1118830C Semiconductor memory device and method for detecting and using the same
08/20/2003CN1118708C Test method of integrated circuit device using double-side clock technique
08/19/2003US6609222 Methods and circuitry for built-in self-testing of content addressable memories
08/19/2003US6608785 Method and apparatus to ensure functionality and timing robustness in SOI circuits
08/19/2003US6608784 Non-volatile semiconductor memory device
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