| Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524) | 
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| 07/03/2003 | WO2003054888A2 Non-volatile memory and method for operating a non-volatile memory | 
| 07/03/2003 | WO2003054565A1 Compact ate with timestamp system | 
| 07/03/2003 | US20030126534 Distributed interface for parallel testing of multiple devices using a single tester channel | 
| 07/03/2003 | US20030126532 Integrated circuit | 
| 07/03/2003 | US20030126529 Wafer burn-in test mode circuit | 
| 07/03/2003 | US20030126528 Method for creating defect management information in an recording medium, and apparatus and medium based on said method | 
| 07/03/2003 | US20030126527 Method for creating defect management information in an recording medium, and apparatus and medium based on said method | 
| 07/03/2003 | US20030126526 On-board testing circuit and method for improving testing of integrated circuits | 
| 07/03/2003 | US20030126525 Semiconductor device, method of testing the same and electronic instrument | 
| 07/03/2003 | US20030126524 Semiconductor storage unit | 
| 07/03/2003 | US20030126513 Secure EEPROM memory comprising an error correction circuit | 
| 07/03/2003 | US20030126512 System and method of improving memory yield in frame buffer memory using failing memory location | 
| 07/03/2003 | US20030126490 Method and apparatus for managing timestamps when storing data | 
| 07/03/2003 | US20030125896 Processing semiconductor devices having some defective input-output pins | 
| 07/03/2003 | US20030123314 Method and apparatus for verification of a gate oxide fuse element | 
| 07/03/2003 | US20030123309 Semiconductor integrated circuit | 
| 07/03/2003 | US20030123301 Semiconductor memory device post-repair circuit and method | 
| 07/03/2003 | US20030123286 Method of managing a defect in a flash memory | 
| 07/03/2003 | US20030123278 Flexible multibanking interface for embedded memory applications | 
| 07/03/2003 | US20030122587 256 meg dynamic random access memory | 
| 07/03/2003 | US20030121584 Process for manufacturing semiconductor device | 
| 07/02/2003 | EP1324349A2 System and method of improving memory yield in frame buffer memory using failing memory location | 
| 07/02/2003 | EP1324348A1 Autotesting method of a memory cells matrix, particularly of the non-volatile type | 
| 07/02/2003 | EP1323167A1 A method for performing write and read operations in a passive matrix memory, and apparatus for performing the method | 
| 07/02/2003 | EP1323039A1 Method for operating a processor-controlled system | 
| 07/02/2003 | CN1427954A Circuit arrangement for detecting malfunction | 
| 07/02/2003 | CN1427467A Method of release charge accumulation of non volatile storage structure | 
| 07/02/2003 | CN1427420A RAM high speed test control circuit and its testing method | 
| 07/02/2003 | CN1427418A Semiconductor storage device, data processor and method for determining frequency | 
| 07/02/2003 | CN1427417A Semiconductor storage device and information apparatus | 
| 07/02/2003 | CN1113366C Method and device for automatic determination of required high voltage for programming/erasing EEPROM | 
| 07/02/2003 | CN1113294C Method and apparatus for correcting multilevel cell memory by using error locating codes | 
| 07/02/2003 | CN1113293C Method and apparatus for detecting and concealing data errors in stored digital data | 
| 07/01/2003 | US6587996 Device and method for increased fault coverage using scan insertion techniques around synchronous memory | 
| 07/01/2003 | US6587983 Apparatus and method of testing a semiconductor device | 
| 07/01/2003 | US6587982 Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling | 
| 07/01/2003 | US6587980 Intelligent binning for electrically repairable semiconductor chips | 
| 07/01/2003 | US6587979 Partitionable embedded circuit test system for integrated circuit | 
| 07/01/2003 | US6587978 Circuit and method for varying a pulse width of an internal control signal during a test mode | 
| 07/01/2003 | US6587975 Semiconductor test apparatus and method | 
| 07/01/2003 | US6587804 Method and apparatus providing improved data path calibration for memory devices | 
| 07/01/2003 | US6587387 Device and method for testing mask ROM for bitline to bitline isolation leakage | 
| 07/01/2003 | US6587386 Semiconductor memory having multiple redundant columns with offset segmentation boundaries | 
| 07/01/2003 | US6587384 Multi-function serial I/O circuit | 
| 07/01/2003 | US6586961 Structure and method of repair of integrated circuits | 
| 07/01/2003 | US6586823 Semiconductor device that can have a defective bit found during or after packaging process repaired | 
| 06/26/2003 | WO2003052768A1 Semiconductor test apparatus | 
| 06/26/2003 | WO2003052767A1 Semiconductor testing apparatus | 
| 06/26/2003 | US20030120985 Method and apparatus for memory self testing | 
| 06/26/2003 | US20030120974 Programable multi-port memory bist with compact microcode | 
| 06/26/2003 | US20030120891 Device and method for associating information concerning memory cells of a memory with an external memory | 
| 06/26/2003 | US20030119213 Pre-erase manufacturing method | 
| 06/26/2003 | US20030117882 Semiconductor memory device | 
| 06/26/2003 | US20030117881 Multi-mode synchronouos memory device and method of operating and testing same | 
| 06/26/2003 | US20030117879 Semiconductor memory device and method for selecting multiple word lines in a semiconductor memory device | 
| 06/26/2003 | US20030117872 Semiconductor memory device | 
| 06/26/2003 | US20030117871 Memory module with test mode | 
| 06/26/2003 | US20030117868 Measurement of timing skew between two digital signals | 
| 06/26/2003 | US20030117867 Semiconductor memory device | 
| 06/26/2003 | US20030117858 Semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other | 
| 06/26/2003 | US20030117856 Memory devices with page buffer having dual registers and method of using the same | 
| 06/26/2003 | US20030117853 Operation verification system and adaptive control system | 
| 06/26/2003 | US20030117847 Nonvolatile semiconductor memory device | 
| 06/26/2003 | US20030117829 Circuit device having a fuse | 
| 06/26/2003 | US20030117826 Semiconductor memory device and electronic instrument | 
| 06/26/2003 | US20030116786 Semiconductor memory test device | 
| 06/26/2003 | US20030116763 Semiconductor integrated circuit device | 
| 06/25/2003 | EP1321945A1 Semiconductor storage device and information apparatus | 
| 06/25/2003 | EP1320852A2 Control apparatus for testing a random access memory | 
| 06/25/2003 | CN1112707C Semiconductor memory element | 
| 06/25/2003 | CN1112706C Semiconductor memory capable of imaging bad block | 
| 06/24/2003 | US6584592 Semiconductor testing apparatus for testing semiconductor device including built in self test circuit | 
| 06/24/2003 | US6584589 Self-testing of magneto-resistive memory arrays | 
| 06/24/2003 | US6584588 System signalling schemes for processor & memory module | 
| 06/24/2003 | US6584584 Method and apparatus for detecting errors in a First-In-First-Out buffer | 
| 06/24/2003 | US6584579 Method of writing, erasing, and controlling memory for memory device | 
| 06/24/2003 | US6584577 System for measuring response time of a circuit by determining the time difference between the earlier and the later clock pulses applied to the circuit | 
| 06/24/2003 | US6584037 Memory device which samples data after an amount of time transpires | 
| 06/24/2003 | US6584024 Memory testing | 
| 06/24/2003 | US6584023 System for implementing a column redundancy scheme for arrays with controls that span multiple data bits | 
| 06/24/2003 | US6584022 Semiconductor memory device with simultaneous data line selection and shift redundancy selection | 
| 06/24/2003 | US6584020 Semiconductor memory device having intermediate voltage generating circuit | 
| 06/24/2003 | US6584017 Method for programming a reference cell | 
| 06/24/2003 | US6584014 Nonvolatile storage system | 
| 06/24/2003 | US6584007 Circuit and method for testing a ferroelectric memory device | 
| 06/19/2003 | WO2003050818A1 Flash array implementation with local and global bit lines | 
| 06/19/2003 | WO2003050552A1 Testing current perpendicular to plane giant magnetoresistance multilayer devices | 
| 06/19/2003 | US20030115537 Weighted error/erasure correction in a multi-track storage medium | 
| 06/19/2003 | US20030115528 Semiconductor memory device capable of failure analysis with system in operation | 
| 06/19/2003 | US20030115519 Parallel testing system for semiconductor memory devices | 
| 06/19/2003 | US20030115518 Memory device and method for redundancy/self-repair | 
| 06/19/2003 | US20030115502 Method of restoring encapsulated integrated circuit devices | 
| 06/19/2003 | US20030115425 Method of verifying a system in which a plurality of master devices share a storage region | 
| 06/19/2003 | US20030115417 Methods and apparatus for loading CRC values into a CRC cache in a storage controller | 
| 06/19/2003 | US20030115009 Method and apparatus for generating a data pattern for simultaneously testing multiple bus widths | 
| 06/19/2003 | US20030112696 Semiconductor memory device | 
| 06/19/2003 | US20030112695 Dynamic ram-and semiconductor device | 
| 06/19/2003 | US20030112693 Apparatus and method for parallel programming of antifuses | 
| 06/19/2003 | US20030112689 Semiconductor memory device for realizing external 8K Ref/internal 4K Ref standard without lengthening the refresh cycle | 
| 06/19/2003 | US20030112676 Semiconductor integrated circuit device with internal potential generating circuit allowing external tuning of internal power supply potential |