Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation
Patents for G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
12/2003
12/03/2003CN1129913C Anti fuse for programming, repair circuit having programming apparatus and fabrication method of anti fuse
12/03/2003CN1129911C Synchronous type semiconductor storage
12/02/2003US6658637 Semiconductor device trimming method, semiconductor device trimming apparatus, and method for creating semiconductor device trimming table
12/02/2003US6658621 System and method for silent data corruption prevention due to next instruction pointer corruption by soft errors
12/02/2003US6658612 Test signal generating circuit of a semiconductor device with pins receiving signals of multiple voltage levels and method for invoking test modes
12/02/2003US6658611 Programmable built-in self-test system for semiconductor memory device
12/02/2003US6658610 Compilable address magnitude comparator for memory array self-testing
12/02/2003US6658609 Semiconductor memory device with a test mode
12/02/2003US6658608 Apparatus and method for testing ferroelectric memories
12/02/2003US6658604 Method for testing and guaranteeing that skew between two signals meets predetermined criteria
12/02/2003US6657915 Wordline driver for ensuring equal stress to wordlines in multi row address disturb test and method of driving the wordline driver
12/02/2003US6657907 Column repair circuit of semiconductor memory
12/02/2003US6657904 Semiconductor device
12/02/2003US6657896 Fail number detecting circuit of flash memory
12/02/2003US6657531 Fuse circuit using capacitors as fuse elements
12/02/2003US6656751 Self test method and device for dynamic voltage screen functionality improvement
12/02/2003US6656647 Method for examining structures on a wafer
11/2003
11/27/2003WO2003098638A1 Fault tolerant computer
11/27/2003WO2003098633A2 Content addressable memory (cam) with error checking and correction
11/27/2003US20030221153 Shmoo plot evaluation method with a relief analysis
11/27/2003US20030221149 Test configuration with automatic test machine and integrated circuit and method for determining the time behavior of an integrated circuit
11/27/2003US20030221148 Failure analysis method that allows high-precision failure mode classification
11/27/2003US20030221147 Compression test circuit
11/27/2003US20030221146 Method and apparatus to data log at-speed March C+ memory BIST
11/27/2003US20030221145 System and method for testing memory arrays
11/27/2003US20030221144 Devices for storing and accumulating defect information, semiconductor device and device for testing the same
11/27/2003US20030220759 Fail analyzer
11/27/2003US20030218932 Semiconductor device
11/27/2003US20030218931 Semiconductor memory device requiring refresh operation
11/27/2003US20030218929 Circuit configuration having a flow controller, integrated memory device, and test configuration having such a circuit configuration
11/27/2003US20030218928 Semiconductor memory device having a circuit for fast operation
11/27/2003US20030218925 Methods for storing data in non-volatile memories
11/27/2003US20030218920 Highly compact Eprom and flash EEprom devices
11/27/2003US20030218493 Antifuse Circuit
11/27/2003US20030218481 Differential current evaluation circuit and sense amplifier circuit for evaluating a memory state of an SRAM semiconductor memory cell
11/27/2003US20030218217 Semiconductor memory device
11/27/2003US20030218216 Semiconductor memory module
11/27/2003US20030218182 Strees-controlled dielectric integrated circuit
11/27/2003DE10219649C1 Differentielle Strombewerterschaltung und Leseverstärkerschaltung zum Bewerten eines Speicherzustands einer SRAM-Halbleiterspeicherzelle Differential current evaluation circuit and sense amplifier circuit for evaluating a state of a memory SRAM semiconductor memory cell
11/26/2003EP1365419A1 Self-repair method for non volatile memory device with erasing/programming failure detection, and non volatile memory device therefor
11/26/2003EP1365413A2 Differential current sense amplifier circuit and sense amplifier circuit for evaluating the memory state of a SRAM semiconductor memory cell
11/26/2003EP1365326A1 Method of controlling flash memory
11/26/2003CN1458678A Integrated circuit chip and wafer and its producing and detecting method
11/26/2003CN1129141C Flexible fuse placement semiconductor memory in redundant semiconductor memory area
11/26/2003CN1129076C Test method of high speed cache memory of multiprocessor system
11/25/2003US6654919 Automated system for inserting and reading of probe points in silicon embedded testbenches
11/25/2003US6654904 Method for registering, in a defect map, addresses of defective sectors of a data recording medium
11/25/2003US6654300 Semiconductor memory device having internal circuit screening function
11/25/2003US6654299 Semiconductor device
11/25/2003US6654298 Semiconductor memory device
11/25/2003US6654290 Flash memory device with cell current measuring scheme using write driver
11/25/2003US6654286 Nonvolatile semiconductor memory device detecting sign of data transformation
11/25/2003US6653957 SERDES cooperates with the boundary scan test technique
11/20/2003WO2003096353A1 Method and apparatus for improving the reliability of the reading of integrated circuit fuses
11/20/2003WO2003096039A1 Tester system having a multi-purpose memory
11/20/2003WO2003009304A3 Duty-cycle-efficient sram cell test
11/20/2003WO2002089133A3 Data integrity error handling in a redundant storage array
11/20/2003US20030217323 Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data
11/20/2003US20030217322 Variable hamming error correction for a one-time-programmable-ROM
11/20/2003US20030217317 Method and apparatus for displaying test results and recording medium
11/20/2003US20030217314 Semiconductor memory device with data scramble circuit
11/20/2003US20030217313 Method and auxiliary device for testing a RAM memory circuit
11/20/2003US20030214865 Semiconductor memory having multiple redundant columns with offset segmentation boundaries
11/20/2003US20030214845 Semiconductor integrated circuit device having data input/output configuration variable
11/20/2003US20030214278 Internal power supply voltage control apparatus having two internal power supply reference voltage generating circuits
11/20/2003US20030213988 Semiconductor memory module
11/20/2003US20030213954 Defective cell remedy method capable of automatically cutting capacitor fuses within the fabrication process
11/20/2003US20030213953 Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same
11/20/2003DE10217710C1 Halbleiterschaltung mit Fuses und Ausleseverfahren für Fuses Semiconductor circuit with fuses and selection procedures for Fuses
11/20/2003DE10214885C1 Verfahren und Teststruktur zur Bestimmung von Widerstandwerten an mehreren zusammengeschalteten Widerständen in einer integrierten Schaltung The method and test structure for the determination of resistance values ​​at a plurality of interconnected resistors in an integrated circuit
11/19/2003EP1363132A2 A method and device for testing of configuration memory cells in programmable logic devices (PLDS)
11/19/2003EP0811989B1 A method and apparatus for testing an integrated circuit memory array
11/19/2003CN1457100A Semiconductor memory
11/18/2003US6651212 Recording/reproduction device, semiconductor memory, and memory card using the semiconductor memory
11/18/2003US6651204 Modular architecture for memory testing on event based test system
11/18/2003US6651203 On chip programmable data pattern generator for semiconductor memories
11/18/2003US6651201 Programmable memory built-in self-test combining microcode and finite state machine self-test
11/18/2003US6651196 Semiconductor device having test mode entry circuit
11/18/2003US6651032 Setting data retention thresholds in charge-based memory
11/18/2003US6651024 Method for automatic testing PCMCIA cards
11/18/2003US6651022 Semiconductor device capable of test mode operation
11/18/2003US6650592 Data processing system, method, and product for automatically performing timing checks on a memory cell using a static timing tool
11/18/2003US6650584 Full stress open digit line memory device
11/18/2003US6650583 Test circuit device capable of identifying error in stored data at memory cell level and semiconductor integrated circuit device including the same
11/18/2003US6650582 Semiconductor memory device
11/18/2003US6650581 Semiconductor memory device, and method for testing the same
11/18/2003US6650580 Method for margin testing
11/18/2003US6650579 Semiconductor device having test and read modes and protection such that ROM data reading is prevented in the test mode
11/18/2003US6650578 Semiconductor storage device and setting method thereof
11/18/2003US6650577 Integrated semiconductor memory having memory cells in a plurality of memory cell arrays and method for repairing such a memory
11/18/2003US6650576 Semiconductor memory and memory board therewith
11/18/2003US6650570 Non-volatile semiconductor memory
11/18/2003US6650562 System and method for determining the logic state of a memory cell in a magnetic tunnel junction memory device
11/18/2003US6649984 Logic-merged memory
11/18/2003US6649931 Semiconductor wafer, semiconductor chip, semiconductor device and method for manufacturing semiconductor device
11/13/2003WO2003093845A2 Semiconductor test system having multitasking algorithmic pattern generator
11/13/2003WO2003079362A3 Circuit arrangement for sensing and evaluating a charge state and rewriting the latter to a memory cell
11/13/2003US20030212939 Method and apparatus for selecting the operational mode of an integrated circuit
11/13/2003US20030212935 Circuit and method for accelerating the test time of a serial access memory device
11/13/2003US20030212934 Debug port for on-die dram
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